I have just started to learn fpga "programming" with Verilog, using a Lattice IceStick development board (iCE40HX1K FPGA). As an exercise, I have copied a uart example I found on the Internet. This simply receives ascii data on an input and re-transmits it on an output pin. However, when I view the output on a scope, I am seeing regular positive glitches when the signal is low. I was expecting the output trace to be a time shifted version of the input trace, and am trying to understand what is causing the glitches shown.

The screen shot below shows the output (yellow trace) for an input of an ascii character 'e' (blue trace) @115200 baud.

I have also tested this on a Devantech board (iceFUN iCE40-HX8K FPGA) with the same result. It would appear that the output pin is going high impedance on the bit transitions. In addition to the scope trace, I have included the script for the fpga transmit module.

Trace (yellow) showing glitches on uart Tx output, uart input is in blue.

// YouTube : Verilog, FPGA, Serial Com: Overview + Example
// https://www.youtube.com/watch?v=Wsou_zhCEYQ&t=1293s
// By hhp3
// Example Verilog code for a UART transmitter.
// Date: April 2024
// Updated: June 2026

module uart_tx
# (parameter CLKS_PER_BIT = 543)
(
input           clock,
input           i_data_avail,
input [7:0]     i_data_byte,
output reg      o_active,
output reg      o_tx,
output reg      o_done
);

localparam IDLE_STATE       = 2'b00;
localparam START_STATE      = 2'b01;
localparam SEND_BIT_STATE   = 2'b10;
localparam STOP_STATE       = 2'b11;

reg [1:0]   state       = 0;
reg [$clog2(CLKS_PER_BIT):0] counter;
reg [2:0]   bit_index   = 0;
reg [7:0]   data_byte   = 0; 

always @(posedge clock)
begin

    case (state)

    IDLE_STATE :
        begin
            o_tx    <= 1;
            o_done  <= 0;
            counter <= 0;
            bit_index <= 0;
        
            if (i_data_avail == 1)
                begin
                    o_active  <= 1;
                    data_byte <= i_data_byte;
                    state <= START_STATE;
                end
            else
                state <= IDLE_STATE;
                o_active  <= 0;
        end

    // Send Start bit_index
    START_STATE :
        begin
            o_tx <= 0;
            // Wait CLKS_PER_BIT-1 clock cycles for start bit to finish
            if (counter < CLKS_PER_BIT-1)
                begin
                counter <= counter + 16'b1;
                state   <= START_STATE;
                end
            else
                begin
                counter <= 0;
                state <= SEND_BIT_STATE;
                end
        end

    // Wait CLKS_PER_BIT-1 clock cycles for each data bit to finish.
    SEND_BIT_STATE :
        begin
            o_tx <= data_byte[bit_index];
            if (counter < CLKS_PER_BIT-1)
                begin
                counter <= counter + 16'b1;
                state   <= SEND_BIT_STATE;
                end
            else
                begin
                    counter <= 0;
                    // Check if we have sent out all bits
                    if (bit_index < 7)
                        begin
                            bit_index <= bit_index + 3'b1;
                            state <= SEND_BIT_STATE;
                        end
                    else
                        begin
                            bit_index <= 0;
                            state <= STOP_STATE;
                        end
                end
        end

    // Send Stop bit
    STOP_STATE :
    begin
        o_tx <= 1;
        // Wait CLKS_PER_BIT-1 clock cycles for stop bit to finish.
        if (counter < CLKS_PER_BIT-1)
            begin
                counter <= counter + 16'b1;
                state   <= STOP_STATE;
            end
        else
            begin
                o_done  <= 1;   // Raise o_done for final clock cycle.
                state   <= IDLE_STATE;
                o_active <= 0;
            end         
    end
    
    default :
        state <= IDLE_STATE;

    endcase
end
endmodule