I'm struggling to meet TSCO timing when my internal I3C clock is < 333MHz. According to I3C spec 1.1.1 TSCO needs to be <12ns. If you are >12ns you need to report this additional delay. I'd like to meet TSCO timing with frequencies <333MHz.

After synchronizing SCL + edge detect + time to react to the event the required frequency is 333MHz to meet the spec.

Aside from having a second clock domain for sampling SCL/SDA are there other techniques to edge detect an async signal so I don't have to pay the 2-3 cycle penalty of a synchronizer?