I'm working on a pretty simple 5-stage pipelined processor in VHDL that I'm going to implement on an FPGA. The design works fine without a cache, but I've run into some issues adding a cache to my design. I think the issue stems from the fact that any sizeable cache on an FPGA will need to be implemented in block RAM, and therefore be synchronous/have a 1 cycle delay. The existing resources I have found online all have async instruction memories feeding into an IF/ID register, while for me the output of the instruction cache is effectively the IF/ID register in the design.

The major issue I am running into is how to stall the PC counter on a cache miss, without unnecessarily stalling the PC during a hit and causing the same instruction to be output twice. Say the PC is set to PC=0x04, which causes a miss. My current cache just says the output is not valid, until it receives and outputs the data. The issue is that in the same cycle we receive and output PC=0x04, the PC is still set to 0x04. So the instruction cache tries to read and output that instruction again. I've done all sorts of work arounds to try and fix this, but I fail on edge cases and it seems like this is clearly not the way to go about it. I feel like I am missing a critical part of the design, or some sort of proper interface between the PC counter and the cache that would avoid all these issues. Any help?

Thanks