PMC counters [0..3] and [4..7] inequality in Intel 11th gen. Rocket Lake (RKL) CPU
04:15 18 Feb 2026

I'm using Intel 11th gen. Rocket Lake (RKL) CPU to test some code performance with performance monitoring counters (PMC) technique. I have turned off CPU hyper-threading (in BIOS). Thus, there are 8 programmable PMC available (would be 4 for each thread at hyper-threading turned on). But, for some PMC events upper half of the counters (counters [4..7]) don't work (returns zero). For example, events related to instruction decode queue (IDQ): IDQ.MITE_UOPS, IDQ.DSB_UOPS, LSD.UOPS while placing in counters [4..7] don't work, but work in counters [0..3]. Other events, e.g. UOPS_RETIRED.SLOTS (uops fused) or MACHINE_CLEARS.COUNT work in any counter.

Regardless of how front-end components shared between threads, after hyper-threading turn off all resources must be solely attached to one thread.

Why do PMC [4..7] not count the events mentioned? Do you have related experience?

Thanks!

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