I am currently designing a hardware accelerator for ShuffleNet V2 implemented on an FPGA (e.g., targeting a ZCU104 board). I am preparing to evaluate and report the power efficiency (e.g., GOPS/W) of my design, but I am unsure about the standard methodology for power measurement in this context.
My dilemma is whether I should isolate and report only the FPGA chip's power consumption (Dynamic + Static power of the logic used by the accelerator), or if I should report the entire evaluation board's power consumption (including external RAM, PHYs, and onboard peripherals).
My specific questions are:
When benchmarking an FPGA CNN accelerator against other platforms (like embedded GPUs or other FPGAs) in academic or industrial contexts, what is the accepted standard for reporting power?
If isolating the chip's power is the standard, is using the software power estimator (e.g., Vivado Power Report) sufficient, or is hardware-level measurement via power rails (e.g., PMBus/shunt resistors) strictly required?
Any references to standard benchmarking methodologies or established practices would be highly appreciated.