Suppose I want encrypted RAM, in a system with processor cache. One would hope or assume that reads/writes to main memory are contiguous and cacheline-sized.

If RAM is encrypted, the best scenario is that each read/write is aligned so that one is reading or writing one full ciphertext and not having to dynamically determine how the memory region relates to existing encrypted blocks, i.e. having to fetch adjacent memory to decrypt a full ciphertext on a read, or having to fetch adjacent memory to decrypt and re-encrypt on a write.

I don't know anything about memory, so my questions are:

• Are all reads/write to main memory in contiguous, aligned, cacheline-sized chunks?

• If not, is there a way to force this to be the case at a low level?

• Who is in charge of such things? The processor? Compiler? Operating system (if it exists)?