VHDL INOUT on fpga
05:59 16 Dec 2025

I'm trying to write and read from the same IO

when i used this code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity main is
    Port ( clk : in STD_LOGIC;
           btn : in STD_LOGIC; -- button to start operation
           MAinout : inout STD_LOGIC; -- inout data
           MA : out STD_LOGIC -- output 
           );
end main;

architecture Behavioral of main is
begin
    MAinout <= 'Z';
    MA <= MAinout;
end Behavioral;

it worked,

but when i added a write to the inout it resulted with '0'

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity main is
    Port ( clk : in STD_LOGIC;
           btn : in STD_LOGIC; -- button to start operation
           MAinout : inout STD_LOGIC; -- inout data
           MA : out STD_LOGIC -- output 
           );
end main;

architecture Behavioral of main is
begin
    MAinout <= 'Z' when btn='0' else '1';
    MA <= MAinout;
end Behavioral;

in this updated code it stopped reading and whenever button wasnt pressed its value was stuck at '0'

why is it happening? is there a problem with my code or something else?

vhdl fpga vivado inout