While reading about demand paging, I can see it mentioned in several sources (e.g. http://www.expertsmind.com/questions/name-the-hardware-to-support-demand-paging-30176232.aspx) that we need hardware support for valid / invalid bit for each entry in the page table. However, I'm unable to wrap my head around what that hardware support would look like. As per my understanding,

1. Page table itself is a software-based construct i.e. it has 4-byte / 8-byte (depending on addressing scheme / architecture etc) entries which are present in RAM.
2. The valid / invalid bit is separate from the 4-byte / 8-byte used for each entry of the page table so it's not like out of 4-bytes of a page table entry, we're using 31 bits to store the frame number and 1-bit for valid / invalid bit.

So in summary my question is - what does hardware support for valid / invalid bit look like? If it can vary across implementations / architectures, could you share any particular implementation's details?