I have a VHDL entity with a generic parameter list. The architecture to this entity calculates several constants, which are needed to create the intended functionality.

Is it possible to access one of these constants from outside?

Example 1:
Let's say there is a FIFO that decides based on DEPTH and OUTREG what the best implementation is (register based, SRL based or BlockRAM based). Depending on this the minimum delay through the FIFO can vary from 1 to 2 cycles.

Example 2:
Consider the same FIFO to be cross clock compatible. Now the min delay depends also on the choosen sync circuits and the frequency difference.

Example 3:
A division entity needs N cycles to calculate a div b. N depends on BITS, RADIX, OUTREG, IS_SIGNED, ...

Further let's say each entity has a MIN_DELAY constant of type NATURAL which is of interest for other instances.

E.g. the instantiating entity needs to know how long it must at least wait for a result.

I can think of 2 solutions, but I think neither is a nice one.

Solution 1:
I could store the algorithmn for the computation in a package so it's globally accessable. But this is against the encapsulation principle :). The outside world only needs to know the delay value not the algorithmn.

Solution 2:
I could use a valid bit. That's always a good solution in dynamic, adaptive or pipelined systems, but this bit can not be used at synthesis time for further choices or optimizations.

Possible solution 3:
VHDL has the ability to define new attributes, but can they be accessed?

Example entity: alu_div:

constant MIN_DELAY : NATURAL := BITS / log2(RADIX) + 2;
attribute DELAY   : NATURAL;
attribute DELAY of alu_div : entity is MIN_DELAY;

Example top:

mydiv : entity work.alu_div
   generic map (....)
   port map (....);

blk : block
  constant my : NATURAL := mydiv'delay;
begin
  ....
end block;

NEW: Possible solution 4:
I found this SE question, where Jim Lewis noted that hierarchical references should also work with constants.
alias MY_DELAY is <>;
Get internal signals of vhdl design in ncvhdl (alternative to modelsim's signal spy)