Module inputs without type
09:40 01 Apr 2011

I've encountered in an example for a SystemVerilog code declaration of inputs and outputs for a module without stating their type, e.g., logic, wire...

module mat_to_stream (
  input [2:0] [2:0] [2:0] a,b,
  input newdata,
  input rst, clk,
  output [2:0] [7:0] A_out, B_out);
  //...rest of code...

What is the difference between stating logic and not stating any type?

verilog system-verilog