Verilog 4-bit comparator structural model
01:59 12 Oct 2020

I would like to design a 4-bit comparator as a structural model using a 2-bit comparator.

As shown in the attached picture, after giving initial values ​​to each of Gt_I, Eq_I, and Lt_I, you need to design a 4-bit comparator as a structural model of a 2-bit comparator.

The code I've tried is a syntax error in assigning the initial values ​​of Gt_I, Eq_I, and Lt_I. I want to know a solution.

<2bit>

module Comparator_new(a, b, Gt_I, Eq_I, Lt_I, Gt_O, Eq_O, Lt_O);

input [1:0] a;
input [1:0] b;
input Gt_I, Eq_I, Lt_I;
output Gt_O, Eq_O, Lt_O;

assign Gt_O = ~(a[1] & ~b[1] | ~a[1] & b[1]) & a[0] & ~b[0] | a[1] & ~b[1];
assign Eq_O = ~(a[0] & ~b[0] | ~a[0] & b[0]) & ~(a[1] & ~b[1] | ~a[1] & b[1]);
assign Lt_O = ~(a[1] & ~b[1] | ~a[1] & b[1]) & ~a[0] & b[0] | ~a[1] & b[1];
endmodule

<4bit>

module Comparator_stru(a, b, Gt_I, Eq_I, Lt_I, Gt, Eq, Lt);

input [3:0] a;
input [3:0] b;
input Gt_I = 2'b00;
input Eq_I = 2'b01;
input Lt_I = 2'b00;
output Gt, Eq, Lt;

wire x, y, z;

Comparator_new c0(.a(a), .b(b), .Gt_I(Gt_I), .Eq_I(Eq_I), .Lt_I(Lt_I), .Gt_O(x), .Eq_O(y), .Lt_O(z));
Comparator_new c1(.a(a), .b(b), .Gt_I(x), .Eq_I(y), .Lt_I(z), .Gt_O(Gt), .Eq_O(Eq), .Lt_O(Lt));

assign Gt_O = ~(a[3] & ~b[3] | ~a[3] & b[3]) & a[2] & ~b[2] | a[3] & ~b[3];
assign Eq_O = ~(a[2] & ~b[2] | ~a[2] & b[2]) & ~(a[3] & ~b[3] | ~a[3] & b[3]);
assign Lt_O = ~(a[3] & ~b[3] | ~a[3] & b[3]) & ~a[2] & b[2] | ~a[3] & b[3];
endmodule
`timescale 1ns/10ps

module tb_Comparator_stru;
reg a, b;
wire Gt, Eq, Lt;

Comparator_stru tb(.a(a), .b(b), .Gt(Gt), .Eq(Eq), .Lt(Lt));

initial
begin
    $dumpfile("test_Comparator_stru_out.vcd");
    $dumpvars(-1, tb);
    $monitor("%b", Gt);
    $monitor("%b", Eq);
    $monitor("%b", Lt);
end

initial
    begin
        a = 2'b00; b = 2'b00;
    #50 a = 2'b01; b = 2'b00;
    #50 a = 2'b01; b = 2'b01;
    #50 a = 2'b01; b = 2'b10;
    #50 a = 2'b10; b = 2'b10;
    #50 a = 2'b11; b = 2'b10;
    #50 a = 2'b11; b = 2'b11;
    #50;
    end
endmodule

diagram

verilog