I am trying to implement a 4x1 multiplexer in Verilog. I want to connect enable (en) as a port which input '1' (high) can turn ON the MUX and '0'(low) turn OFF this multiplexer.

Please suggest some modifications in my code.

module mux_4_to_1 (
    input d,c,b,a,      // Inputs
    input s1,s0,        // Select Lines
    input en,           // enable
    output reg y        // output
    );

always @ (*)
begin
    case (s0 | s1)
    2'b00 : y <= a;
    2'b01 : y <= b;
    2'b10 : y <= c;
    2'b11 : y <= d;
    default : y <= 0;
    endcase
end
endmodule