The following code below generates this error message:

verilog always_comb imposes the restriction that it contains one and only one event control and no blocking timing controls

always_comb begin
if (sig_a) begin
    @(posedge sig_b); // wait for a sig_b posedge event
    @(negedge sig_b); // then wait for a sig_b negedge event
    event_true=1;   
end

if (event_true)begin
    @((sig_c==1)&&(sig_a==0)); //wait for sig_a to deassert and sig_c assert event to be true
    yes =1;
end
else yes =0;
end

Why does the combi logic procedural block generate this error?

And would an always block with @ event wait be synthesizable?