I'm preparing a program in Verilog. I have a problem with implementing a short pulse that will occur every time on a rising edge of slow clock and disappear on the rising edge of the fast clock.

Below I paste the code I wrote, which gives me such a pulse, but unfortunately it appears only once on the first edge and never occurs again.

reg cnt_write_bit1, cnt_write_bit2; 
initial cnt_write_bit1 = 0;
initial cnt_write_bit2 = 0;
reg cnt_write_fifo;
initial cnt_write_fifo = 0; 

always @ (posedge clk_1kHz)
begin : WRITE_FIFO
    if (cnt_write_fifo)
    begin
        cnt_write_bit1 <= 0;
    end
    else
    begin
        cnt_write_bit1 <= 1;
    end
end

always @ (posedge clk_50MHz)
begin : STOP_WRITE_FIFO
    if (cnt_write_fifo)
    begin
        cnt_write_bit2 <= 0;
    end
    else //if (!cnt_write_bit1)
    begin
        cnt_write_bit2 <= 1;
    end
end

always @ (cnt_write_bit1, cnt_write_bit2)
begin 
    if (cnt_write_bit1 && cnt_write_bit2)
    begin 
        cnt_write_fifo <= 1;
    end
    else if (!cnt_write_bit2)
    begin
        cnt_write_fifo <= 0;
    end
end

On the simulation it looks like this:

The pulse on the "cnt_write_fifo" signal should be repeatable on every rising edge of slow clock, but unfortunately it is not.

I will be grateful for any help.