Verilog $signed(), what is this?
00:40 13 Dec 2015

I am just getting started with verilog. I was looking at some example code for a floating multiply someone wrote and I came across this...

if ($signed(b_e == -1023) && (b_m == 0)) begin
            z[63] <= 1;
            z[62:52] <= 2047;
            z[51] <= 1;
            z[50:0] <= 0;
            state <= put_z;
          end

I am just wondering what the $signed is. I tried googling it but I just got a bunch of results about signed math (not about this function). I thought functions that begin with a $ were only for test-bench code. What does this function do? Also is there a place where I can get a list of the verilog functions?

verilog