I got the problem with using the input's value in Verilog. I write:

module reg_vector (INPUT, ICLK, IENBL, NR, OUT);
parameter k = 6;
parameter n = 3;
input [(8*k)-1:0] INPUT;
input ICLK;
input IENBL;
input [n-1:0] NR;

reg [n-1:0] temp;
output reg [7:0] OUT;

always @(temp, posedge ICLK)
begin
    if (IENBL)
        begin
            OUT = INPUT[temp*8 : temp*8+8];
        end
end

endmodule

But got the error:

Error (10734): Verilog HDL error at reg_vector.v(25): temp is not a constant

How should I fix it?