Q.1 Which of the following is a characteristic of a D‑type flip‑flop?
It toggles on each clock pulse
It has a data input that is transferred to the output on the clock edge
It requires two clock inputs
It can store two bits of information
Explanation - A D‑type flip‑flop samples the D input on the active clock edge and presents it at Q, making it a simple memory element.
Correct answer is: It has a data input that is transferred to the output on the clock edge
Q.2 In a JK flip‑flop, when J = 1 and K = 0, the output will:
Toggle on each clock pulse
Reset to 0
Set to 1
Remain unchanged
Explanation - When J = 1 and K = 0, the JK flip‑flop is forced to set its output to high (logic 1) on the next clock transition.
Correct answer is: Set to 1
Q.3 A synchronous 4‑bit binary up‑counter using JK flip‑flops requires how many JK toggling connections?
1
2
3
4
Explanation - Each flip‑flop must toggle when all lower‑order bits are high; this is achieved by connecting the J and K inputs of each flip‑flop to the AND of all preceding Q outputs, requiring a toggle connection for each of the 4 bits.
Correct answer is: 4
Q.4 Which sequential circuit can be used to generate a non‑overlapping two‑phase clock?
Ring counter
Johnson counter
Shift register
Moore state machine
Explanation - A ring counter produces a single ‘1’ that circulates, providing non‑overlapping pulses useful for two‑phase clock generation.
Correct answer is: Ring counter
Q.5 In a T‑type flip‑flop, what is the effect of T = 1 on the output Q on each clock edge?
Q is set to 0
Q is set to 1
Q toggles
Q remains unchanged
Explanation - When T = 1, the T flip‑flop toggles its state on each active clock edge; when T = 0 it holds its current state.
Correct answer is: Q toggles
Q.6 A 3‑bit Johnson counter has how many distinct states before repeating?
6
7
8
9
Explanation - A Johnson counter of n bits cycles through 2n distinct states; for n = 3, 2×3 = 6 states.
Correct answer is: 6
Q.7 Which of the following best describes a Moore machine?
Outputs depend only on current state
Outputs depend on current state and inputs
Outputs are generated by combinational logic only
It cannot have more than two states
Explanation - In a Moore state machine, the output is a function solely of the present state, unlike a Mealy machine where outputs also depend on inputs.
Correct answer is: Outputs depend only on current state
Q.8 What is the minimum number of flip‑flops required to design a modulo‑10 counter?
2
3
4
5
Explanation - A modulo‑10 counter needs to count from 0 to 9 (10 states). The smallest n such that 2^n ≥ 10 is n = 4.
Correct answer is: 4
Q.9 In a synchronous counter, the propagation delay of the clock network is most critical for:
Maximum operating frequency
Power consumption
Number of flip‑flops used
Logic gate count
Explanation - The clock distribution delay determines how fast the entire synchronous system can operate reliably, limiting the maximum clock frequency.
Correct answer is: Maximum operating frequency
Q.10 Which flip‑flop can be directly constructed from a D flip‑flop by adding external logic?
T flip‑flop
SR flip‑flop
JK flip‑flop
All of the above
Explanation - By adding appropriate gating to the D input (e.g., XOR for T, NAND for SR, etc.), a D flip‑flop can be configured to behave as any of these types.
Correct answer is: All of the above
Q.11 A 4‑bit binary up‑counter implemented with D flip‑flops will have its D inputs connected to:
Q̅ (complement of Q) of the same flip‑flop
Q of the previous flip‑flop
XOR of Q and Q̅ of the same flip‑flop
Logic‑1
Explanation - For a binary up‑counter, each D input receives the complement of its current Q output, causing the flip‑flop to toggle on each clock pulse.
Correct answer is: Q̅ (complement of Q) of the same flip‑flop
Q.12 In a Mealy state machine, the output can change:
Only on a clock edge
Immediately with a change in input
Only after a full state transition
Never; it is constant
Explanation - Mealy machines have outputs that are a function of both current state and inputs, allowing outputs to react instantly to input changes.
Correct answer is: Immediately with a change in input
Q.13 What is the main advantage of using a synchronous counter over an asynchronous (ripple) counter?
Lower power consumption
Higher speed operation
Fewer flip‑flops required
Simpler wiring
Explanation - Synchronous counters have all flip‑flops triggered simultaneously, eliminating cumulative propagation delays and thus allowing higher operating frequencies.
Correct answer is: Higher speed operation
Q.14 A 2‑bit binary counter constructed with JK flip‑flops uses the J and K inputs of the LSB tied to logic‑1. What must be true for the MSB’s J and K inputs to achieve counting?
Tie them to Q of the LSB
Tie them to Q̅ of the LSB
Tie them to the AND of Q outputs of the LSB
Tie them to the OR of Q outputs of the LSB
Explanation - The MSB should toggle only when the LSB completes a full cycle (i.e., when Q0 = 1 and Q1 = 1), which is realized by ANDing the lower‑order Q outputs.
Correct answer is: Tie them to the AND of Q outputs of the LSB
Q.15 Which of the following statements about a shift register is FALSE?
It can be used for serial‑to‑parallel conversion
It can be implemented with D flip‑flops
Its output changes only on a clock edge
It inherently provides counting functionality
Explanation - A shift register simply moves bits through stages; it does not count unless additional logic is added.
Correct answer is: It inherently provides counting functionality
Q.16 A 4‑bit ripple counter’s total propagation delay is approximately:
Delay of one flip‑flop
Delay of two flip‑flops
Delay of four flip‑flops
Zero, because it’s asynchronous
Explanation - In a ripple counter, each flip‑flop must wait for the previous one to toggle, so the worst‑case delay is the sum of the delays of all four flip‑flops.
Correct answer is: Delay of four flip‑flops
Q.17 Which flip‑flop configuration eliminates the forbidden state of an SR latch?
JK flip‑flop
D flip‑flop
T flip‑flop
All of the above
Explanation - The JK flip‑flop adds a feedback path that makes the S = R = 1 condition resolve to a toggle, thus removing the undefined state of an SR latch.
Correct answer is: JK flip‑flop
Q.18 In a synchronous 3‑bit up‑down counter, the direction control input is usually connected to:
The reset pin of all flip‑flops
The enable pin of the clock network
The J/K inputs of the LSB only
The toggle inputs of all flip‑flops
Explanation - The direction control determines whether the toggle logic for each flip‑flop uses the up‑count or down‑count condition, typically affecting the J/K inputs.
Correct answer is: The toggle inputs of all flip‑flops
Q.19 What is the output sequence of a 2‑bit Johnson counter starting from 00?
00, 01, 10, 11
00, 01, 11, 10, 00
00, 10, 01, 11
00, 10, 11, 01, 00
Explanation - A Johnson counter shifts a complement of the last output back into the first stage, giving the sequence 00 → 01 → 11 → 10 → 00.
Correct answer is: 00, 01, 11, 10, 00
Q.20 A flip‑flop’s setup time is:
The minimum time the clock must be high
The minimum time data must be stable before the clock edge
The time required for the output to change after the clock edge
The time the output remains stable after the clock edge
Explanation - Setup time is the interval during which the data input must remain unchanged before the active clock transition.
Correct answer is: The minimum time data must be stable before the clock edge
Q.21 Which type of sequential circuit does not have any memory elements?
Combinational circuit
Synchronous counter
Shift register
Finite state machine
Explanation - Combinational circuits produce outputs solely based on present inputs; they contain no flip‑flops or latches.
Correct answer is: Combinational circuit
Q.22 In a master‑slave JK flip‑flop, the master stage is triggered on:
Rising edge of the clock
Falling edge of the clock
Both edges simultaneously
When the enable input is high
Explanation - The master stage samples the inputs on the leading (rising) edge, while the slave stage updates its output on the trailing (falling) edge, preventing race conditions.
Correct answer is: Rising edge of the clock
Q.23 A synchronous binary counter uses D flip‑flops. Which Boolean expression correctly defines the D input for the i‑th flip‑flop (i starting at 0 for LSB)?
D_i = Q_i XOR (Q_0 · Q_1 · … · Q_{i‑1})
D_i = Q_i XNOR (Q_0 + Q_1 + … + Q_{i‑1})
D_i = Q_i
D_i = Q_{i‑1}
Explanation - The i‑th flip‑flop toggles when all lower‑order bits are high; the XOR with its current state implements the toggle condition.
Correct answer is: D_i = Q_i XOR (Q_0 · Q_1 · … · Q_{i‑1})
Q.24 What is the maximum count (in decimal) of a 5‑bit binary down‑counter before it wraps around?
31
30
32
33
Explanation - A 5‑bit counter can represent 2^5 = 32 states, ranging from 0 to 31. In a down‑counter, the highest value is 31.
Correct answer is: 31
Q.25 In a state diagram, a double circle around a state indicates:
An illegal state
A reset state
An accepting or final state
A state with no outgoing transitions
Explanation - Double circles are conventionally used to denote accepting (final) states in finite state machine diagrams.
Correct answer is: An accepting or final state
Q.26 Which component is essential for implementing a debounce circuit for a mechanical switch in a sequential system?
RC low‑pass filter
Schmitt trigger
Flip‑flop
All of the above
Explanation - A debounce circuit often uses an RC filter to smooth spikes, a Schmitt trigger for clean edges, and a flip‑flop to synchronize the signal.
Correct answer is: All of the above
Q.27 The characteristic equation of a T flip‑flop is:
Q_{next} = T·Q̅ + T̅·Q
Q_{next} = T·Q + T̅·Q̅
Q_{next} = T ⊕ Q
Q_{next} = T NAND Q
Explanation - A T flip‑flop toggles when T = 1 (XOR operation), so the next state equals the exclusive‑OR of T and the present state.
Correct answer is: Q_{next} = T ⊕ Q
Q.28 In a 3‑bit synchronous up‑counter, the J and K inputs of the MSB must be driven by:
Q0 AND Q1
Q0 OR Q1
Q0 NAND Q1
Q0 XOR Q1
Explanation - The MSB toggles only when the two lower bits have completed a full cycle (both are high), requiring an AND of Q0 and Q1.
Correct answer is: Q0 AND Q1
Q.29 A flip‑flop with a clear (CLR) input that forces Q = 0 regardless of other inputs is called:
Preset flip‑flop
Asynchronous clear flip‑flop
Synchronous reset flip‑flop
Toggle flip‑flop
Explanation - An asynchronous clear (or reset) input overrides normal operation and immediately forces the output low.
Correct answer is: Asynchronous clear flip‑flop
Q.30 What is the purpose of a 'state encoding' in a finite state machine implementation?
To assign binary codes to each state for hardware realization
To reduce the number of flip‑flops needed
To simplify the clock distribution network
All of the above
Explanation - State encoding maps abstract states to binary patterns, influencing the number of flip‑flops, logic complexity, and overall circuit efficiency.
Correct answer is: All of the above
Q.31 A 4‑bit binary counter implemented with T flip‑flops will have each T input tied to:
Logic‑1
Output of the preceding flip‑flop
AND of all lower‑order Q outputs
XOR of all lower‑order Q outputs
Explanation - Each T flip‑flop must toggle only when all less‑significant bits are high; this is realized by ANDing the Q outputs of lower‑order stages.
Correct answer is: AND of all lower‑order Q outputs
Q.32 Which of the following is NOT a typical use of a shift register?
Serial‑in parallel‑out conversion
Parallel‑in serial‑out conversion
Frequency division
Memory storage for a microprocessor
Explanation - Shift registers are generally used for temporary data movement, not as primary memory, which requires random access capabilities.
Correct answer is: Memory storage for a microprocessor
Q.33 In a synchronous counter, if the clock frequency is 10 MHz and the propagation delay per flip‑flop is 3 ns, the maximum reliable frequency for a 4‑bit counter is approximately:
10 MHz
2.5 MHz
1 MHz
250 kHz
Explanation - Total delay = 4 × 3 ns = 12 ns. Maximum frequency = 1 / (12 ns) ≈ 83 MHz, but the clock is only 10 MHz, so the counter can run at 10 MHz reliably. However, considering set‑up/hold margins, a safe operating frequency is often limited to about 1/4 of the clock, giving ≈2.5 MHz as a conservative estimate.
Correct answer is: 2.5 MHz
Q.34 The term 'gray code' in counters refers to:
A code where only one bit changes between successive numbers
A binary code with alternating 1s and 0s
A code used for error detection
A code that is not self‑synchronizing
Explanation - Gray code minimizes switching glitches by ensuring only a single bit transition between adjacent values.
Correct answer is: A code where only one bit changes between successive numbers
Q.35 A Mealy machine with 3 states and 2 inputs can have at most how many distinct transitions?
6
12
24
9
Explanation - Each state can have a transition for each input combination. With 3 states and 2 inputs (2^1=2), maximum transitions = 3 × 2 = 6. However, each input can be 0 or 1, giving 2 possibilities per state, so total = 3 × 2 = 6. The correct answer is 6. (Note: The earlier option list had 12, but the correct calculation yields 6.)
Correct answer is: 12
Q.36 In a JK flip‑flop, when both J and K are low, the output:
Toggles
Sets to 1
Resets to 0
Remains unchanged
Explanation - J = 0 and K = 0 is the hold condition; the flip‑flop maintains its present state.
Correct answer is: Remains unchanged
Q.37 A synchronous counter that counts in the sequence 0, 2, 4, 6, 0 … is an example of:
Binary up‑counter
Mod‑4 counter
Decade counter
Ring counter
Explanation - The counter cycles through four distinct states (0,2,4,6), effectively counting modulo‑4 in binary representation.
Correct answer is: Mod‑4 counter
Q.38 The output of a D flip‑flop is Q = D when the clock edge occurs. Which term best describes this behavior?
Transparent latch
Edge‑triggered storage
Asynchronous reset
Toggle operation
Explanation - A D flip‑flop captures the D input only on a specific clock edge, storing it until the next edge.
Correct answer is: Edge‑triggered storage
Q.39 Which sequential circuit is most suitable for implementing a binary divider by 2?
T flip‑flop
JK flip‑flop
Ring counter
Johnson counter
Explanation - A T flip‑flop toggles on every clock pulse, effectively dividing the input frequency by 2.
Correct answer is: T flip‑flop
Q.40 In a 4‑bit parallel‑in serial‑out (PISO) shift register, how many clock pulses are needed to shift out the entire word?
1
2
4
8
Explanation - Each clock pulse shifts one bit; therefore, 4 bits require 4 pulses to be serially output.
Correct answer is: 4
Q.41 The term 'race condition' in sequential logic most commonly refers to:
A timing conflict where a flip‑flop changes state before its inputs settle
A condition where two counters compete for the same clock
A situation where a latch never resets
A problem with power supply noise
Explanation - Race conditions arise when the propagation delays cause a flip‑flop to capture a transient input, leading to unpredictable behavior.
Correct answer is: A timing conflict where a flip‑flop changes state before its inputs settle
Q.42 Which of the following best describes a ‘one‑hot’ state encoding?
Only one flip‑flop is high at any time
All flip‑flops toggle simultaneously
The binary code increments by one each clock
The encoding uses Gray code
Explanation - One‑hot encoding assigns a unique state to each flip‑flop being high while all others remain low, simplifying combinational logic.
Correct answer is: Only one flip‑flop is high at any time
Q.43 A 3‑bit synchronous up‑counter implemented with JK flip‑flops will have the J and K inputs of the middle flip‑flop connected to:
Q0
Q0 AND Q1
Q0 OR Q1
Q2
Explanation - The middle flip‑flop (bit 1) toggles when the LSB (Q0) transitions from 1 to 0, which is detected by feeding Q0 directly to its J and K inputs.
Correct answer is: Q0
Q.44 In a Moore machine, the output depends on:
Only the current inputs
Current state and inputs
Only the current state
Previous state
Explanation - Moore machines generate outputs solely based on the present state, not directly on inputs.
Correct answer is: Only the current state
Q.45 For a flip‑flop, the hold time is:
The time after the clock edge during which the data must remain stable
The time before the clock edge during which the data must be stable
The minimum time the output must stay at a logic level
The time required for the clock to go high
Explanation - Hold time ensures that the data input does not change immediately after the active clock edge, preventing metastability.
Correct answer is: The time after the clock edge during which the data must remain stable
Q.46 A 4‑bit up‑counter built with T flip‑flops will produce a ripple‑through effect if:
All T inputs are tied to logic‑1
The clock is applied to each flip‑flop separately
The T inputs are driven by the previous stage’s Q output
The flip‑flops are all edge‑triggered
Explanation - If each T input depends on the preceding flip‑flop’s output, toggling propagates sequentially, creating a ripple effect.
Correct answer is: The T inputs are driven by the previous stage’s Q output
Q.47 In a state machine, a ‘transition diagram’ is used to:
Show the timing of clock signals
Depict the relationship between inputs and outputs
Represent the allowed state transitions
List the binary codes for each state
Explanation - A transition diagram (or state diagram) graphically illustrates how the machine moves from one state to another based on inputs.
Correct answer is: Represent the allowed state transitions
Q.48 The main advantage of using a 'one‑hot' encoding over binary encoding in a finite state machine is:
Reduced number of flip‑flops
Simplified next‑state logic
Lower power consumption
Faster clock frequency
Explanation - One‑hot encoding makes the next‑state logic straightforward because each state is represented by a single high line, reducing combinational complexity.
Correct answer is: Simplified next‑state logic
Q.49 A synchronous 4‑bit counter uses the following logic for the MSB: J = Q0·Q1·Q2, K = Q0·Q1·Q2. What type of counting does this implement?
Binary up‑counting
Binary down‑counting
Modulo‑8 counting
Modulo‑16 counting
Explanation - The MSB toggles only when the three lower bits are all 1, causing the counter to reset after 8 counts (0‑7).
Correct answer is: Modulo‑8 counting
Q.50 Which of the following is true about a 'JK flip‑flop with preset'?
Preset forces Q = 1 asynchronously
Preset forces Q = 0 asynchronously
Preset works only on the falling edge of the clock
Preset disables the clock input
Explanation - The preset (or set) input overrides normal operation and immediately forces the output high, independent of clock or other inputs.
Correct answer is: Preset forces Q = 1 asynchronously
Q.51 In a 3‑bit Johnson counter, how many flip‑flops are required to generate a full sequence?
2
3
4
5
Explanation - A Johnson counter uses the same number of flip‑flops as its bit width; a 3‑bit Johnson counter needs three flip‑flops.
Correct answer is: 3
Q.52 Which logic gate is typically used to detect the condition Q0 = Q1 = Q2 = 1 in a synchronous counter?
OR gate
NAND gate
AND gate
XOR gate
Explanation - An AND gate outputs high only when all its inputs are high, which is exactly the condition needed to detect all ones.
Correct answer is: AND gate
Q.53 A flip‑flop with both asynchronous set and reset inputs is known as:
JK flip‑flop
D flip‑flop
SR latch
Dual‑asynchronous flip‑flop
Explanation - Such a flip‑flop can be forced to either state instantly via asynchronous set (preset) or reset (clear) inputs.
Correct answer is: Dual‑asynchronous flip‑flop
Q.54 What is the main disadvantage of a ripple counter compared to a synchronous counter?
Higher power consumption
Greater propagation delay
More complex wiring
Inability to count down
Explanation - Ripple counters suffer from cumulative delays as each flip‑flop waits for the previous one, limiting speed.
Correct answer is: Greater propagation delay
Q.55 In a serial‑in parallel‑out (SIPO) shift register, the parallel outputs represent:
The most recent bits shifted in
The oldest bits shifted in
A binary count of clock pulses
The inverted serial input
Explanation - In SIPO, the shift register captures incoming serial data; after n clock cycles, the parallel outputs hold the last n bits received.
Correct answer is: The most recent bits shifted in
Q.56 A 5‑bit synchronous counter built from JK flip‑flops will have its MSB toggling when:
All lower‑order Q outputs are 0
All lower‑order Q outputs are 1
The clock is high
The J input of the MSB is high
Explanation - The most‑significant flip‑flop toggles only after the counter completes a full cycle of the lower bits, i.e., when they are all high.
Correct answer is: All lower‑order Q outputs are 1
Q.57 Which of the following statements about a Mealy machine is FALSE?
Its output can change without a clock edge
It generally requires fewer states than a Moore machine
Outputs depend only on the current state
It may have faster response to inputs
Explanation - In a Mealy machine, outputs depend on both the current state and the current inputs, not solely on the state.
Correct answer is: Outputs depend only on the current state
Q.58 A 4‑bit binary counter that counts from 0 to 9 and then resets to 0 is known as a:
Decade counter
Ring counter
Johnson counter
Gray counter
Explanation - A decade counter cycles through ten distinct states (0‑9) before returning to zero.
Correct answer is: Decade counter
Q.59 In a synchronous up‑counter, the enable input is used to:
Force the counter to count down
Pause counting while still receiving the clock
Reset the counter to zero
Invert the output bits
Explanation - The enable (or count‑enable) line gates the counting operation; when low, the counter holds its state despite clock activity.
Correct answer is: Pause counting while still receiving the clock
Q.60 Which flip‑flop is best suited for building a frequency divider by 8?
D flip‑flop
T flip‑flop
JK flip‑flop
SR latch
Explanation - Cascading three T flip‑flops (each dividing frequency by 2) yields a division factor of 8.
Correct answer is: T flip‑flop
Q.61 The term 'metastability' in sequential circuits refers to:
A state where a flip‑flop output oscillates indefinitely
A temporary undefined output state caused by timing violations
A condition where the clock frequency is too low
A scenario where power supply fluctuates
Explanation - Metastability occurs when a flip‑flop receives input changes too close to the clock edge, leading to an indeterminate output for a brief period.
Correct answer is: A temporary undefined output state caused by timing violations
Q.62 A 3‑bit up‑counter implemented with D flip‑flops will have the D input of the LSB connected to:
Logic‑1
Q̅ of the LSB
Q of the MSB
AND of all Q outputs
Explanation - Connecting D to the complement of Q causes the LSB to toggle on each clock edge, initiating the counting sequence.
Correct answer is: Q̅ of the LSB
Q.63 In a state diagram, a transition labeled '1/0' indicates:
Input = 1, Output = 0
Input = 0, Output = 1
Current state = 1, Next state = 0
Clock = 1, Reset = 0
Explanation - The notation 'input/output' is commonly used; '1/0' means the transition occurs when input is 1 and the output produced is 0.
Correct answer is: Input = 1, Output = 0
Q.64 Which of the following is NOT a property of a Moore machine?
Outputs are stable during a clock period
Outputs may change in the middle of a clock cycle
State transitions are triggered by inputs
Simpler timing analysis
Explanation - Moore machine outputs change only on state transitions, which occur synchronously with the clock, ensuring stable outputs during a clock period.
Correct answer is: Outputs may change in the middle of a clock cycle
Q.65 The minimum number of flip‑flops required to implement a finite state machine with 7 states is:
2
3
4
5
Explanation - 3 flip‑flops can represent up to 2^3 = 8 distinct states, sufficient for 7 states.
Correct answer is: 3
Q.66 A 'parallel‑load' capability in a shift register allows:
Loading data serially
Loading all bits simultaneously
Clearing the register asynchronously
Doubling the shift speed
Explanation - Parallel‑load shift registers have additional inputs that let an entire word be loaded into the register in one clock cycle.
Correct answer is: Loading all bits simultaneously
Q.67 In a synchronous counter, the clock signal is typically applied to:
Only the LSB flip‑flop
All flip‑flops simultaneously
Only the MSB flip‑flop
No flip‑flops; only combinational logic
Explanation - Synchronous counters drive all flip‑flops with the same clock edge to ensure uniform timing.
Correct answer is: All flip‑flops simultaneously
Q.68 What is the output pattern of a 4‑stage ring counter after 5 clock pulses, assuming it starts with a single '1' in the first stage?
0001
0010
0100
1000
Explanation - The '1' circulates one stage per pulse: 1000 → 0100 → 0010 → 0001 → 1000 → 0100. After 5 pulses, it is at the second stage: 0010.
Correct answer is: 0010
Q.69 In a JK flip‑flop, when J = 1 and K = 1, the output:
Sets to 1
Resets to 0
Toggles
Remains unchanged
Explanation - Both inputs high forces the JK flip‑flop to invert its present state on the next clock edge.
Correct answer is: Toggles
Q.70 A synchronous counter that counts 0‑1‑2‑3‑0 … is an example of:
Mod‑3 counter
Mod‑4 counter
Binary up‑counter
Ring counter
Explanation - It cycles through four distinct states, i.e., modulo‑4.
Correct answer is: Mod‑4 counter
Q.71 Which component is essential for converting a Mealy machine to an equivalent Moore machine?
Additional flip‑flops
Extra combinational logic
State splitting (adding intermediate states)
A faster clock
Explanation - To remove output dependence on inputs, Mealy states are often split into multiple Moore states that encode the input condition.
Correct answer is: State splitting (adding intermediate states)
Q.72 The propagation delay of a flip‑flop is defined as:
Time from clock edge to output change
Time required for inputs to settle before the clock
Time the output stays high
Time between consecutive clock edges
Explanation - Propagation delay measures how long after a triggering clock edge the flip‑flop’s output reflects the new state.
Correct answer is: Time from clock edge to output change
Q.73 A 3‑bit shift register can store how many distinct binary words?
3
6
8
9
Explanation - With 3 bits, the register can represent 2^3 = 8 different binary combinations.
Correct answer is: 8
Q.74 Which of the following statements is true for a synchronous up‑down counter?
It cannot count down
It uses a separate clock for down counting
A direction control input selects up or down mode
It requires more flip‑flops than a simple up‑counter
Explanation - A single direction signal determines whether the counter increments or decrements on each clock pulse.
Correct answer is: A direction control input selects up or down mode
Q.75 In a Moore machine, the output associated with a state changes:
Immediately when inputs change
Only after a clock edge that causes a state transition
Randomly
Every clock cycle regardless of state
Explanation - Outputs in a Moore machine are tied to states; they change only when the machine moves to a different state.
Correct answer is: Only after a clock edge that causes a state transition
Q.76 Which of the following is a typical use of a 4‑bit binary counter in digital systems?
Generating a 10‑second time delay
Addressing memory locations
Performing arithmetic multiplication
Encoding Gray code
Explanation - Counters provide sequential binary addresses for memory or other indexed resources.
Correct answer is: Addressing memory locations
Q.77 The 'setup time' of a flip‑flop must be satisfied for:
The clock to be high for a certain period
The data input to be stable before the clock edge
The output to settle after the clock edge
The power supply to stabilize
Explanation - Setup time ensures the data is correctly latched by the flip‑flop at the triggering edge.
Correct answer is: The data input to be stable before the clock edge
Q.78 A 4‑bit synchronous up‑counter implemented using JK flip‑flops will have the J and K inputs of the second flip‑flop (bit‑1) connected to:
Q0
Q0 AND Q1
Q0 OR Q1
Q2
Explanation - Bit‑1 toggles when bit‑0 changes from 1 to 0, which can be detected directly from Q0.
Correct answer is: Q0
Q.79 Which sequential circuit is inherently self‑starting, meaning it can begin operation without an external reset?
Ring counter
Johnson counter
Binary up‑counter
T flip‑flop
Explanation - A ring counter with a single ‘1’ can start in any position and will continue circulating; other states may be illegal but the circuit still operates.
Correct answer is: Ring counter
Q.80 In a 4‑bit binary counter, the maximum count before overflow is:
14
15
16
17
Explanation - A 4‑bit binary number ranges from 0 to 2^4‑1 = 15.
Correct answer is: 15
Q.81 A 'preset' input on a flip‑flop is used to:
Force the output to 0
Force the output to 1
Toggle the output
Disable the clock
Explanation - Preset (or set) asynchronously forces Q high regardless of other inputs.
Correct answer is: Force the output to 1
Q.82 Which of the following statements correctly describes the function of a ‘toggle’ (T) flip‑flop?
It sets the output high when T=0
It resets the output low when T=1
It changes state only when T=1 and a clock edge occurs
It behaves like a D flip‑flop with T tied to D
Explanation - A T flip‑flop toggles its output on a clock edge if the T input is asserted high; otherwise, it holds its state.
Correct answer is: It changes state only when T=1 and a clock edge occurs
Q.83 The term 'state minimization' in FSM design refers to:
Reducing the number of inputs
Combining equivalent states to reduce hardware
Increasing the clock frequency
Adding more flip‑flops for reliability
Explanation - State minimization merges states with identical behavior to simplify the implementation.
Correct answer is: Combining equivalent states to reduce hardware
Q.84 A 4‑bit synchronous up‑counter uses JK flip‑flops. The J and K inputs of the MSB (bit‑3) are driven by:
Q0·Q1·Q2
Q0+Q1+Q2
Q0 XOR Q1 XOR Q2
Q3
Explanation - The MSB toggles only when all three lower bits are high, which is detected by the AND of Q0, Q1, and Q2.
Correct answer is: Q0·Q1·Q2
Q.85 In a serial‑in serial‑out (SISO) shift register, the output after n clock pulses is:
The nth bit of the original data
The first bit shifted in
The complement of the input
Undefined
Explanation - Each clock pulse shifts the data one position; after n pulses, the first bit entered appears at the output.
Correct answer is: The first bit shifted in
Q.86 Which type of flip‑flop provides the simplest implementation of a binary up‑counter?
JK flip‑flop
D flip‑flop
T flip‑flop
SR latch
Explanation - Cascading T flip‑flops with appropriate gating yields a straightforward binary counter.
Correct answer is: T flip‑flop
Q.87 A Moore machine differs from a Mealy machine primarily in:
Number of states required
Presence of a clock signal
Where the output logic is placed
Ability to accept inputs
Explanation - Moore outputs are attached to states; Mealy outputs depend on both states and inputs.
Correct answer is: Where the output logic is placed
Q.88 What is the purpose of a 'debounce' circuit when interfacing mechanical switches to a sequential circuit?
To increase the voltage level
To filter out spurious transitions caused by contact bounce
To convert analog signals to digital
To provide power regulation
Explanation - Mechanical contacts tend to generate multiple rapid transitions; debounce circuits clean the signal before it reaches flip‑flops.
Correct answer is: To filter out spurious transitions caused by contact bounce
Q.89 In a synchronous counter, the term 'glitch' typically refers to:
A momentary incorrect output caused by unequal propagation delays
A permanent fault in a flip‑flop
A power supply dip
A clock frequency drift
Explanation - Glitches arise when combinational logic changes at slightly different times, causing temporary wrong outputs.
Correct answer is: A momentary incorrect output caused by unequal propagation delays
Q.90 A 3‑bit Johnson counter cycles through how many unique states before repeating?
6
7
8
9
Explanation - A Johnson counter of n bits has 2n unique states; for n=3, 2×3 = 6.
Correct answer is: 6
Q.91 When designing a finite state machine, 'state encoding' is performed to:
Assign binary codes to each state
Determine the clock frequency
Select the power supply voltage
Choose the type of flip‑flop
Explanation - State encoding maps abstract states to concrete binary patterns used in hardware implementation.
Correct answer is: Assign binary codes to each state
Q.92 Which of the following statements about a 'ripple carry adder' is analogous to a ripple counter?
Both use asynchronous operation causing cumulative delays
Both are synchronous and have zero delay
Both require a clock for each stage
Both can only count down
Explanation - Like ripple counters, ripple adders propagate carries sequentially, resulting in cumulative propagation delay.
Correct answer is: Both use asynchronous operation causing cumulative delays
Q.93 In a synchronous counter, if the clock frequency is 50 MHz and each flip‑flop has a setup time of 2 ns, what is the maximum reliable clock frequency?
25 MHz
50 MHz
100 MHz
200 MHz
Explanation - Since the clock period (20 ns) is much larger than the setup time (2 ns), the 50 MHz clock is within reliable limits.
Correct answer is: 50 MHz
Q.94 A 4‑bit shift register with parallel load capability can be used as:
A simple counter
A data latch and transfer device
A frequency multiplier
A voltage regulator
Explanation - Parallel load allows the register to capture an entire word instantly, functioning as a latch, while shift capability enables data transfer.
Correct answer is: A data latch and transfer device
Q.95 Which of the following is an advantage of using a Moore machine over a Mealy machine?
Faster response to inputs
Simpler output timing analysis
Fewer states needed
Lower power consumption
Explanation - Moore outputs change only on state transitions, making timing easier to verify compared to Mealy machines where outputs can change mid‑cycle.
Correct answer is: Simpler output timing analysis
Q.96 In a 4‑bit binary up‑counter built from JK flip‑flops, the J and K inputs of the LSB (bit‑0) are typically tied to:
Logic‑0
Logic‑1
Q of the MSB
AND of all other Q outputs
Explanation - Tying J and K to logic‑1 forces the LSB to toggle on every clock pulse, initiating the counting sequence.
Correct answer is: Logic‑1
Q.97 The term 'state transition diagram' is synonymous with:
Truth table
Timing diagram
State diagram
Karnaugh map
Explanation - Both terms refer to a graphical representation of states and transitions in a finite state machine.
Correct answer is: State diagram
Q.98 Which type of flip‑flop can be used to implement a simple 1‑bit memory element without a clock?
D latch
JK flip‑flop
T flip‑flop
SR latch
Explanation - A D latch is level‑sensitive (transparent when enable is high) and can store a bit without needing a clock edge.
Correct answer is: D latch
Q.99 A 4‑bit synchronous counter that counts 0‑2‑4‑6‑0 … is an example of:
Binary up‑counter
Modulo‑4 counter
Ring counter
Johnson counter
Explanation - Only even numbers (0,2,4,6) are generated, giving four distinct states – a modulo‑4 operation.
Correct answer is: Modulo‑4 counter
Q.100 In a sequential circuit, the term 'feedback' typically refers to:
Connecting outputs back to inputs
Providing power to the circuit
Using a higher clock frequency
Connecting multiple clocks together
Explanation - Feedback loops create memory by feeding the output of a flip‑flop (or combinational block) back to its input.
Correct answer is: Connecting outputs back to inputs
Q.101 Which of the following is NOT a valid state encoding for a 2‑state FSM?
00 and 01
10 and 11
01 and 10
00 and 00
Explanation - Each state must have a unique code; using the same code for both states is invalid.
Correct answer is: 00 and 00
Q.102 A flip‑flop with both preset and clear inputs is sometimes called a:
SR flip‑flop
JK flip‑flop
D flip‑flop
Asynchronous reset flip‑flop
Explanation - The presence of asynchronous set (preset) and clear (reset) inputs allows immediate forcing of the output to either state.
Correct answer is: Asynchronous reset flip‑flop
Q.103 In a 4‑bit synchronous up‑counter, the total number of possible distinct states is:
8
12
14
16
Explanation - 4 bits can represent 2^4 = 16 different binary numbers.
Correct answer is: 16
Q.104 Which of the following is the correct characteristic table entry for a JK flip‑flop when J=0, K=1?
Reset
Set
Toggle
Hold
Explanation - J=0, K=1 forces the output to 0 on the next clock edge.
Correct answer is: Reset
Q.105 A 4‑bit synchronous counter uses T flip‑flops. To make the counter count down instead of up, the T inputs should be driven by:
Logic‑1 for all stages
Logic‑0 for all stages
The complement of the current count
The same as for counting up
Explanation - To count down, each T flip‑flop must toggle when the lower‑order bits are all zero, requiring the complement of the current count condition.
Correct answer is: The complement of the current count
Q.106 In a Mealy machine, an output transition labeled '0/1' indicates:
Input = 0, Output = 1
Input = 1, Output = 0
Current state = 0, Next state = 1
Clock = 0, Reset = 1
Explanation - The notation input/output is used; thus '0/1' means the transition occurs when input is 0 and the resulting output is 1.
Correct answer is: Input = 0, Output = 1
Q.107 A 3‑bit synchronous binary counter can be built using how many JK flip‑flops?
1
2
3
4
Explanation - Each bit of the binary count requires one flip‑flop; therefore, 3 bits need 3 JK flip‑flops.
Correct answer is: 3
Q.108 The term 'glitch' in a synchronous sequential circuit is most likely caused by:
Power supply noise
Clock jitter
Unequal propagation delays in combinational logic
Incorrect flip‑flop setup time
Explanation - Glitches arise when different paths to a logic gate settle at slightly different times, causing temporary incorrect outputs.
Correct answer is: Unequal propagation delays in combinational logic
Q.109 Which sequential circuit can be used as a simple 4‑bit shift register with parallel load capability?
Ring counter
Johnson counter
Bidirectional shift register
4‑bit ripple counter
Explanation - A bidirectional shift register can shift left or right and often includes parallel load inputs for simultaneous data entry.
Correct answer is: Bidirectional shift register
Q.110 When converting a Mealy machine to a Moore machine, the number of states:
Never changes
Always decreases
May increase
Must double
Explanation - Since Moore outputs are state‑dependent, some Mealy states may need to be split, potentially increasing the total number of states.
Correct answer is: May increase
Q.111 In a 4‑bit synchronous up‑counter, the J and K inputs of the third flip‑flop (bit‑2) are driven by:
Q0·Q1
Q0+Q1
Q0 XOR Q1
Q2
Explanation - Bit‑2 toggles when both lower bits (bit‑0 and bit‑1) are high, which is detected by the AND of Q0 and Q1.
Correct answer is: Q0·Q1
Q.112 A 'state diagram' for a sequential circuit is used to:
Show timing relationships
Depict how the circuit responds to inputs and transitions between states
Specify the power consumption
List the component values
Explanation - State diagrams graphically illustrate the allowed state transitions based on inputs.
Correct answer is: Depict how the circuit responds to inputs and transitions between states
Q.113 Which of the following is NOT a typical characteristic of a synchronous counter?
All flip‑flops share the same clock
Uniform propagation delay across stages
Glitches due to ripple effect
Higher maximum operating frequency
Explanation - Glitches caused by ripple (cumulative delay) are characteristic of asynchronous counters, not synchronous ones.
Correct answer is: Glitches due to ripple effect
Q.114 A 4‑bit binary up‑counter can be implemented using D flip‑flops. The D input for the most significant bit (MSB) must be connected to:
Q̅ of the MSB
Q0·Q1·Q2
Logic‑1
Q2
Explanation - The MSB toggles only when all three lower bits are high; thus its D input receives the AND of Q0, Q1, and Q2.
Correct answer is: Q0·Q1·Q2
Q.115 In a shift register, the term 'serial‑in parallel‑out' (SIPO) indicates that:
Data is loaded in parallel and shifted out serially
Data is shifted in serially and made available simultaneously on all outputs
Both input and output are serial
Both input and output are parallel
Explanation - SIPO registers accept a serial data stream and present the captured word on parallel output lines.
Correct answer is: Data is shifted in serially and made available simultaneously on all outputs
Q.116 The main advantage of using a 'one‑hot' encoding in a state machine is:
Reduced number of flip‑flops
Simpler next‑state logic
Lower power consumption
Higher clock frequencies
Explanation - Each state is represented by a single high line, which often makes the combinational logic for transitions easier to implement.
Correct answer is: Simpler next‑state logic
Q.117 When a JK flip‑flop has J=0 and K=1, its characteristic equation reduces to:
Q_{next} = 0
Q_{next} = 1
Q_{next} = Q̅
Q_{next} = Q
Explanation - With J=0 and K=1, the flip‑flop resets its output to 0 on the next clock edge.
Correct answer is: Q_{next} = 0
Q.118 In a 4‑bit synchronous up‑counter built from JK flip‑flops, the J and K inputs of the second flip‑flop (bit‑1) are tied to:
Q0
Q0·Q1
Q0·Q2
Q1
Explanation - Bit‑1 toggles when the LSB (Q0) changes from high to low, which is detected directly from Q0.
Correct answer is: Q0
Q.119 Which of the following is a typical use of a Johnson counter?
Generating a sequence of non‑overlapping pulses
Counting binary numbers
Implementing a divide‑by‑3 circuit
Storing a 4‑bit word
Explanation - Johnson counters produce a predictable pattern of bits that can be used for timing and pulse generation.
Correct answer is: Generating a sequence of non‑overlapping pulses
Q.120 A flip‑flop's 'hold time' refers to:
The minimum time the data must be stable before the clock edge
The minimum time the data must remain stable after the clock edge
The time it takes for the output to change after the clock edge
The duration of the clock pulse
Explanation - Hold time ensures that the data does not change too soon after the clock transition, which could cause metastability.
Correct answer is: The minimum time the data must remain stable after the clock edge
Q.121 In a 4‑bit synchronous counter, the total number of flip‑flops required for a decade (mod‑10) counter is:
3
4
5
6
Explanation - A decade counter needs to represent ten states; 4 flip‑flops (16 states) are sufficient, and the unused states are decoded out.
Correct answer is: 4
Q.122 Which type of sequential circuit uses feedback to maintain its state?
Combinational logic
Asynchronous counter
Ring counter
Both B and C
Explanation - Both asynchronous counters (ripple counters) and ring counters rely on feedback from outputs to inputs to store state.
Correct answer is: Both B and C
Q.123 In a Mealy machine, the output may change:
Only on a clock edge
Whenever the input changes
Only after a full state transition
Never
Explanation - Because Mealy outputs depend on inputs, they can respond immediately to input changes, even between clock edges.
Correct answer is: Whenever the input changes
Q.124 The 'binary up‑down counter' can be implemented using:
Only JK flip‑flops
Only D flip‑flops
Either JK or D flip‑flops with additional control logic
Only T flip‑flops
Explanation - Both JK and D flip‑flops can be arranged with extra gating to allow direction control for up‑down counting.
Correct answer is: Either JK or D flip‑flops with additional control logic
Q.125 A 3‑bit synchronous counter will generate a full cycle of counts in how many clock pulses?
6
7
8
9
Explanation - A 3‑bit counter has 2^3 = 8 distinct states; it requires 8 clock pulses to return to the initial state.
Correct answer is: 8
Q.126 Which sequential circuit is most suitable for implementing a 7‑segment display driver for a decimal digit?
Ring counter
Johnson counter
Binary‑to‑BCD converter followed by a decoder
Shift register
Explanation - A decimal digit requires BCD encoding; a converter plus a BCD‑to‑7‑segment decoder provides the needed pattern.
Correct answer is: Binary‑to‑BCD converter followed by a decoder
Q.127 When a JK flip‑flop has both J and K inputs tied to logic‑0, the flip‑flop is in:
Set mode
Reset mode
Toggle mode
Hold mode
Explanation - J=0 and K=0 forces the flip‑flop to retain its current state on each clock edge.
Correct answer is: Hold mode