Q.1 What is the primary purpose of a register in digital electronics?
To store binary data temporarily
To amplify analog signals
To generate clock pulses
To perform logical operations
Explanation - A register is a group of flip‑flops that holds a word of binary information for a short period, typically for use by the CPU.
Correct answer is: To store binary data temporarily
Q.2 A 4‑bit parallel‑load register can be loaded with a new value on every:
Rising edge of the clock
Falling edge of the clock
Negative voltage pulse
Low level of the enable signal
Explanation - Parallel‑load registers are edge‑triggered; the new data is captured on a specific clock transition, usually the rising edge.
Correct answer is: Rising edge of the clock
Q.3 Which type of register shifts its contents to the left on each clock pulse?
Left‑shift register
Right‑shift register
Parallel register
Universal shift register
Explanation - A left‑shift register moves each bit one position toward the MSB (most‑significant bit) on every clock cycle.
Correct answer is: Left‑shift register
Q.4 In a universal shift register, which control inputs determine the operation mode?
Two mode‑select lines (S1, S0)
Three enable lines
Only a clear line
A single direction line
Explanation - Universal shift registers typically use two select inputs to choose between parallel load, shift left, shift right, and hold.
Correct answer is: Two mode‑select lines (S1, S0)
Q.5 How many D flip‑flops are required to implement an 8‑bit register?
8
4
16
2
Explanation - Each D flip‑flop stores one bit, so an 8‑bit register needs eight flip‑flops.
Correct answer is: 8
Q.6 What does the 'clear' input of a register do?
Resets all bits to 0
Loads a preset value
Inverts the stored data
Stops the clock
Explanation - The clear (or reset) line forces every flip‑flop in the register to a known state, typically logic 0.
Correct answer is: Resets all bits to 0
Q.7 Which register is commonly used to hold the address of the next instruction in a CPU?
Program Counter (PC)
Accumulator (ACC)
Instruction Register (IR)
Status Register (SR)
Explanation - The PC stores the memory address of the next instruction to be fetched.
Correct answer is: Program Counter (PC)
Q.8 A 4‑bit shift register is implemented using D flip‑flops. How many clock cycles are required to shift a bit from the least significant position to the most significant position?
3
4
5
6
Explanation - A bit moves one position per clock; moving from LSB to MSB in a 4‑bit register takes 3 shifts.
Correct answer is: 3
Q.9 Which of the following statements about a ring counter is FALSE?
It requires a decoder to generate output bits.
It cycles a single '1' through the register.
It can be built from a shift register with feedback.
It has exactly one high bit at any time.
Explanation - A ring counter's output is directly taken from the register stages; no external decoder is needed.
Correct answer is: It requires a decoder to generate output bits.
Q.10 In a Johnson counter (twisted‑ring counter) with n flip‑flops, how many unique states does it generate?
2n
n
2n – 1
2ⁿ
Explanation - A Johnson counter cycles through 2n distinct states before repeating.
Correct answer is: 2n
Q.11 What is the function of the 'enable' input in a register?
Controls whether the register accepts new data
Selects the direction of shift
Clears the register
Sets the register to a preset pattern
Explanation - When enable is low (or high, depending on design), the register holds its current contents; when active, it can load or shift data.
Correct answer is: Controls whether the register accepts new data
Q.12 Which register type can both shift data left and right, and also load data in parallel?
Universal shift register
Serial‑in‑parallel‑out register
Parallel‑in‑serial‑out register
Ring counter
Explanation - A universal shift register includes control lines to select left shift, right shift, parallel load, or hold.
Correct answer is: Universal shift register
Q.13 A 3‑bit register holds the binary value 101. After a single right‑shift operation (with zero entering the MSB), what is the new value?
010
110
001
100
Explanation - Shifting right inserts 0 at the MSB and moves bits toward the LSB: 101 → 010.
Correct answer is: 010
Q.14 In a synchronous register, all flip‑flops change state:
Simultaneously on a clock edge
One after another
Only when a clear signal is asserted
Randomly
Explanation - Synchronous design ensures all flip‑flops respond to the same clock transition, providing coordinated state changes.
Correct answer is: Simultaneously on a clock edge
Q.15 Which of the following is NOT a typical use of registers in a microprocessor?
Storing intermediate arithmetic results
Generating high‑frequency clock signals
Holding operand addresses
Temporarily buffering input/output data
Explanation - Registers store data; clock generation is performed by oscillators or PLLs, not by registers.
Correct answer is: Generating high‑frequency clock signals
Q.16 A 4‑bit register has an asynchronous clear input. What is the effect of asserting this clear while a clock pulse is occurring?
The register resets immediately, regardless of the clock
The clear is ignored until the next clock edge
Only the most significant bit is cleared
The register toggles its contents
Explanation - Asynchronous clear forces the flip‑flops to 0 instantly, independent of the clock.
Correct answer is: The register resets immediately, regardless of the clock
Q.17 How many unique states can a 5‑bit binary up‑counter (implemented as a register) represent before it wraps around?
32
31
16
64
Explanation - A 5‑bit binary number can represent 2⁵ = 32 distinct values, from 0 to 31.
Correct answer is: 32
Q.18 Which statement best describes a 'parallel‑load' register?
All bits are loaded simultaneously from separate data lines
Bits are shifted one after another on each clock
Only one bit can be loaded at a time
The register can only store a single bit
Explanation - Parallel‑load registers have a data bus that supplies each bit to the corresponding flip‑flop simultaneously.
Correct answer is: All bits are loaded simultaneously from separate data lines
Q.19 In a 4‑bit shift register, what is the effect of connecting the serial output back to the serial input?
It forms a circular shift (ring) register
It creates a parallel‑load register
It disables shifting
It doubles the register length
Explanation - Feedback from output to input makes the bits circulate, producing a ring counter behavior.
Correct answer is: It forms a circular shift (ring) register
Q.20 Which of the following is a characteristic of a 'bidirectional' shift register?
It can shift data either left or right under control signals
It can only shift left
It can only shift right
It cannot shift, only load in parallel
Explanation - Bidirectional shift registers have select lines that determine shift direction.
Correct answer is: It can shift data either left or right under control signals
Q.21 The most significant bit (MSB) of a binary number stored in a register is:
The leftmost bit
The rightmost bit
Always 0
Always 1
Explanation - In conventional binary representation, the MSB is placed at the left end.
Correct answer is: The leftmost bit
Q.22 Which component is essential for implementing a register that can be loaded on the falling edge of the clock?
Negative‑edge‑triggered D flip‑flop
Positive‑edge‑triggered D flip‑flop
JK flip‑flop
SR latch
Explanation - A falling‑edge‑triggered flip‑flop captures data on the transition from high to low.
Correct answer is: Negative‑edge‑triggered D flip‑flop
Q.23 In a 8‑bit register, what is the binary value after loading 10101100 and then performing a left shift with a '0' entering the LSB?
01011000
11010110
00101011
10101100
Explanation - Shifting left discards the MSB and introduces 0 at LSB: 10101100 → 01011000.
Correct answer is: 01011000
Q.24 What is the difference between a 'register' and a 'memory'?
Registers are faster and located inside the CPU; memory is larger and external.
Memory can only store one bit; registers store many bits.
Registers are analog devices; memory is digital.
There is no difference; they are synonyms.
Explanation - Registers provide immediate access to the processor and are implemented with flip‑flops, while memory uses larger arrays of cells and is slower.
Correct answer is: Registers are faster and located inside the CPU; memory is larger and external.
Q.25 A 4‑bit register is used as a counter that increments on each clock pulse. Which logic must be added to the register to achieve counting?
A combinational circuit that generates the next count (binary adder)
A decoder to translate count to one‑hot
A multiplexer to select input data
An extra clear line
Explanation - To make a register count, a binary adder (or incrementer) provides the next state to be loaded each clock cycle.
Correct answer is: A combinational circuit that generates the next count (binary adder)
Q.26 In a 4‑bit shift register with parallel load, what control signal combination typically selects the 'hold' mode (no change)?
S1=0, S0=0
S1=1, S0=1
S1=1, S0=0
S1=0, S0=1
Explanation - Most universal shift registers use S1S0=00 for hold, 01 for shift right, 10 for shift left, 11 for parallel load.
Correct answer is: S1=0, S0=0
Q.27 Which of the following best describes the term 'bit‑slice' in register design?
A modular unit consisting of a flip‑flop and its associated logic for one bit
A slice of memory that holds a byte
A technique to slice the clock signal
A method of reducing power consumption
Explanation - Bit‑slice architecture replicates a single‑bit circuit for each bit of a word, simplifying design of wide registers and ALUs.
Correct answer is: A modular unit consisting of a flip‑flop and its associated logic for one bit
Q.28 What is the maximum frequency at which a 4‑bit register built with D flip‑flops having a propagation delay of 5 ns can operate reliably?
200 MHz
100 MHz
50 MHz
400 MHz
Explanation - Maximum clock frequency ≈ 1 / (propagation delay) = 1 / 5 ns = 200 MHz.
Correct answer is: 200 MHz
Q.29 A 4‑bit register uses a synchronous clear. How many clock cycles are needed to clear the register after the clear signal is asserted?
1
0
2
4
Explanation - With synchronous clear, the register resets on the next active clock edge, requiring one clock cycle.
Correct answer is: 1
Q.30 In a shift register, the term 'serial‑in‑parallel‑out' (SIPO) means:
Data enters one bit at a time and is read out as a parallel word
Data enters as a parallel word and leaves one bit at a time
Data both enters and leaves serially
Data both enters and leaves in parallel
Explanation - SIPO converts a serial stream into a parallel word by accumulating bits in the register.
Correct answer is: Data enters one bit at a time and is read out as a parallel word
Q.31 Which of the following registers is used to hold the result of an arithmetic operation before it is stored back to memory?
Accumulator
Program Counter
Instruction Register
Status Register
Explanation - The accumulator temporarily stores the output of ALU operations.
Correct answer is: Accumulator
Q.32 A 4‑bit register with a 'load' input and a 'shift left' input receives the binary pattern 1010 on its parallel data lines. If the load control is active on the next clock edge, what will be the register content?
1010
0101
0000
1111
Explanation - Parallel load copies the supplied data directly into the register on the active edge.
Correct answer is: 1010
Q.33 In a 4‑bit universal shift register, which control input combination typically selects 'shift right' operation?
S1=0, S0=1
S1=1, S0=0
S1=1, S0=1
S1=0, S0=0
Explanation - Standard encoding: 00‑hold, 01‑shift right, 10‑shift left, 11‑parallel load.
Correct answer is: S1=0, S0=1
Q.34 What is the main advantage of using a register file (multiple registers) in a microprocessor?
Provides fast, simultaneous access to several operands
Reduces the need for clock signals
Eliminates the need for an ALU
Increases the size of external memory
Explanation - A register file allows the CPU to read/write several registers in one clock cycle, speeding up instruction execution.
Correct answer is: Provides fast, simultaneous access to several operands
Q.35 A register is said to be 'edge‑triggered' rather than 'level‑triggered'. What does this imply?
It changes state only on a clock transition, not while the clock is high or low.
It changes state as long as the clock stays high.
It ignores the clock completely.
It toggles on every clock level.
Explanation - Edge‑triggered devices respond to the rising or falling edge of the clock pulse, providing precise timing.
Correct answer is: It changes state only on a clock transition, not while the clock is high or low.
Q.36 How many flip‑flops are needed to implement a 16‑word deep, 8‑bit wide register file (with separate read/write ports)?
128
256
64
32
Explanation - Each word has 8 bits → 8 flip‑flops per word. 16 words × 8 = 128 flip‑flops.
Correct answer is: 128
Q.37 In a shift register, the term 'serial‑out' (SO) refers to:
The bit that exits the register on each clock pulse
The most significant bit of the parallel output
A control line that enables loading
The clock input
Explanation - Serial‑out provides the least‑significant (or most‑significant) bit after each shift.
Correct answer is: The bit that exits the register on each clock pulse
Q.38 Which of the following describes a 'tri‑state' buffer often used with registers for bus sharing?
It can be in high, low, or high‑impedance (Z) state
It provides three times the normal drive strength
It can store three bits per cell
It toggles between two states only
Explanation - Tri‑state buffers allow multiple devices to share a bus without contention.
Correct answer is: It can be in high, low, or high‑impedance (Z) state
Q.39 When using a D flip‑flop to build a register, the D input of each flip‑flop is connected to:
The corresponding data line or the output of the previous flip‑flop (for shifting)
The clock line directly
The clear line
The power supply
Explanation - In a shift register, each D input receives either external data (parallel load) or the Q output of the preceding stage.
Correct answer is: The corresponding data line or the output of the previous flip‑flop (for shifting)
Q.40 A register that can be cleared asynchronously and loaded synchronously is called:
Asynchronous‑clear, synchronous‑load register
Synchronous‑clear, asynchronous‑load register
Dual‑edge register
Ring register
Explanation - The clear (reset) acts independently of the clock, while loading respects the clock edge.
Correct answer is: Asynchronous‑clear, synchronous‑load register
Q.41 In a 4‑bit shift register, after loading 1101 and performing two right‑shift operations (with zeros entering the MSB), what is the final content?
0011
0110
0001
1100
Explanation - 1101 → shift right → 0110 → shift right → 0011.
Correct answer is: 0011
Q.42 What is the typical purpose of the 'load' (LD) control pin in a register?
To enable parallel loading of data on the next clock edge
To reset the register to zero
To select shift direction
To generate the clock signal
Explanation - When LD is asserted, the register captures the external parallel data on the following active clock edge.
Correct answer is: To enable parallel loading of data on the next clock edge
Q.43 Which register is used to store the status flags (zero, carry, overflow) after an arithmetic operation?
Status Register (SR)
Program Counter (PC)
Instruction Register (IR)
Accumulator (ACC)
Explanation - The status register holds condition codes that indicate the result of the previous operation.
Correct answer is: Status Register (SR)
Q.44 A register file with two read ports and one write port is said to have:
Dual‑port read capability
Triple‑port operation
Single‑port design
No simultaneous access
Explanation - Two independent read ports allow two operands to be fetched in the same cycle, while a single write port stores the result.
Correct answer is: Dual‑port read capability
Q.45 If a 4‑bit register is implemented with master‑slave flip‑flops, how many clock edges are required to complete a data transfer?
Two (one for master, one for slave)
One
Four
Zero
Explanation - Master‑slave arrangement captures data on one edge and transfers it to the slave on the opposite edge.
Correct answer is: Two (one for master, one for slave)
Q.46 In a 4‑bit register, which binary pattern represents the decimal number 9?
1001
0110
1010
1100
Explanation - Binary 1001 equals 1·2³ + 0·2² + 0·2¹ + 1·2⁰ = 8 + 0 + 0 + 1 = 9.
Correct answer is: 1001
Q.47 A register that can both store data and perform logical operations on its contents without external ALU is called:
Arithmetic‑Logic Register (ALR)
Shift Register
Counter Register
Instruction Register
Explanation - ALRs incorporate combinational logic (e.g., adders, XOR) within the register for on‑the‑fly computation.
Correct answer is: Arithmetic‑Logic Register (ALR)
Q.48 What is the main limitation of using a simple shift register as a memory device?
Access to a specific word requires sequential shifting
It cannot store more than one bit
It consumes excessive power
It requires a large number of external pins
Explanation - Shift registers are serial in nature; random access is not possible without additional control logic.
Correct answer is: Access to a specific word requires sequential shifting
Q.49 A 4‑bit register is built using edge‑triggered D flip‑flops with a setup time of 2 ns and a hold time of 1 ns. What is the minimum clock period required?
3 ns
2 ns
1 ns
5 ns
Explanation - Clock period must be at least setup + hold = 2 ns + 1 ns = 3 ns.
Correct answer is: 3 ns
Q.50 Which type of register is used to hold the address of a memory location for indirect addressing?
Index Register
Program Counter
Accumulator
Status Register
Explanation - An index register adds an offset to a base address, enabling indirect memory access.
Correct answer is: Index Register
Q.51 In a parallel‑load register, why is a 'load enable' signal required?
To prevent accidental overwriting of data during normal operation
To generate the clock signal
To clear the register
To shift data
Explanation - Load enable ensures that data is only captured when intended, otherwise the register holds its previous value.
Correct answer is: To prevent accidental overwriting of data during normal operation
Q.52 A 4‑bit register is connected to a 4‑bit adder to form a simple accumulator. After the accumulator holds 0110 and the adder adds 0011, what will the accumulator contain after loading the sum?
1001
0101
1011
1111
Explanation - 0110 (6) + 0011 (3) = 1001 (9). The accumulator loads the result on the next clock edge.
Correct answer is: 1001
Q.53 What is the purpose of a 'clock gating' circuit in a register file?
To reduce dynamic power by disabling the clock to inactive registers
To increase the clock frequency
To invert the clock polarity
To generate multiple clock phases
Explanation - Clock gating shuts off the clock to parts of the circuit that are not in use, saving power.
Correct answer is: To reduce dynamic power by disabling the clock to inactive registers
Q.54 A 4‑bit register receives the binary pattern 1011 on its data lines while the 'load' signal is low. What will be the content after the next clock edge?
Remains unchanged
1011
0000
1111
Explanation - If load is inactive, the register retains its previous value.
Correct answer is: Remains unchanged
Q.55 How many distinct states does a 3‑bit Johnson counter cycle through before repeating?
6
8
4
12
Explanation - A Johnson counter of n bits produces 2n distinct states; for n=3, 2×3 = 6.
Correct answer is: 6
Q.56 In a register built from edge‑triggered D flip‑flops, what is the effect of a metastable condition?
The output may oscillate or settle to an undefined value
The register will clear automatically
The clock frequency will double
The register will become a counter
Explanation - Metastability occurs when data changes too close to the clock edge, leading to unpredictable output.
Correct answer is: The output may oscillate or settle to an undefined value
Q.57 A register with a 'hold' control line is said to be:
Transparent when hold is de‑asserted
Always shifting
Never able to load data
Only capable of serial input
Explanation - When hold is inactive, the register passes data through or retains its current state depending on design.
Correct answer is: Transparent when hold is de‑asserted
Q.58 What is the binary representation of the decimal number 15 in a 4‑bit register?
1111
1010
0111
1100
Explanation - Binary 1111 equals 1·2³ + 1·2² + 1·2¹ + 1·2⁰ = 8+4+2+1 = 15.
Correct answer is: 1111
Q.59 A 4‑bit register is used as a down‑counter. Which logic must be added to decrement the count on each clock pulse?
A binary subtractor (or adder with two's complement)
A decoder
A multiplexer
A shift register
Explanation - Subtracting 1 each cycle can be implemented by adding the two's complement of 1 (i.e., 1111) to the current value.
Correct answer is: A binary subtractor (or adder with two's complement)
Q.60 In a 4‑bit register with an asynchronous preset input, what value is loaded when the preset is asserted?
All bits become 1
All bits become 0
The register holds its current value
The register toggles each bit
Explanation - Asynchronous preset (or set) forces each flip‑flop's output to logic high immediately.
Correct answer is: All bits become 1
Q.61 Which of the following best defines 'propagation delay' in the context of a register?
The time taken for a change at the input to appear at the output
The time between two clock edges
The time required to power up the register
The time needed to clear the register
Explanation - Propagation delay measures the latency of signal transition through the flip‑flop circuitry.
Correct answer is: The time taken for a change at the input to appear at the output
Q.62 A register that can be accessed simultaneously by multiple processors without conflict typically uses:
Dual‑port or multi‑port architecture
Ring counter design
Serial‑in‑parallel‑out configuration
Asynchronous clear only
Explanation - Dual‑port registers provide independent read/write ports, allowing concurrent access.
Correct answer is: Dual‑port or multi‑port architecture
Q.63 What is the function of a 'bias' (or 'pre‑charge') circuit in some high‑speed registers?
To reduce the time needed for the flip‑flop to reach a valid logic level
To increase the voltage supply
To provide an additional data line
To generate random numbers
Explanation - Pre‑charging speeds up the transition of internal nodes, improving overall register performance.
Correct answer is: To reduce the time needed for the flip‑flop to reach a valid logic level
Q.64 In a 4‑bit shift register, what is the effect of connecting the serial input to a constant logic ‘1’ while continuously shifting left?
The register will fill with ones from the LSB side
The register will clear to zero
The register will remain unchanged
The register will generate a pulse train
Explanation - Each left shift pushes existing bits toward MSB and inserts a ‘1’ at the LSB, eventually making all bits ‘1’.
Correct answer is: The register will fill with ones from the LSB side
Q.65 A 4‑bit register is used in a microcontroller to store the result of a bitwise AND operation between two 4‑bit operands. Which internal component is essential for this operation?
A 4‑bit AND gate array
A binary counter
A shift register
A multiplexer
Explanation - Bitwise AND requires a gate per bit that combines the two operands before the result is stored.
Correct answer is: A 4‑bit AND gate array
Q.66 What is the term for a register that can hold both the address and the data for a memory operation (combined address‑data register)?
Memory Buffer Register (MBR)
Program Counter (PC)
Instruction Register (IR)
Accumulator (ACC)
Explanation - The MBR (also called Memory Data Register) temporarily stores data being transferred to/from memory.
Correct answer is: Memory Buffer Register (MBR)
Q.67 If a 4‑bit register is clocked at 50 MHz, what is the maximum time available for the data to become stable before the next clock edge?
20 ns
10 ns
5 ns
2 ns
Explanation - Period = 1 / 50 MHz = 20 ns; this is the time between successive clock edges.
Correct answer is: 20 ns
Q.68 Which of the following statements about 'synchronous' registers is true?
All state changes occur on defined clock edges
They can change state at any time
They do not use a clock signal
They are always slower than asynchronous registers
Explanation - Synchronous design ensures deterministic timing by tying all transitions to the clock.
Correct answer is: All state changes occur on defined clock edges
Q.69 In a 4‑bit universal shift register, which control line(s) are typically used to enable the 'parallel load' function?
Both mode select lines set to ‘1’ (S1=1, S0=1)
Both mode select lines set to ‘0’ (S1=0, S0=0)
Only S1=1
Only S0=1
Explanation - Standard universal shift register encoding uses 11 for parallel load.
Correct answer is: Both mode select lines set to ‘1’ (S1=1, S0=1)
Q.70 A register that can be written to by multiple sources without causing bus contention typically employs:
Tri‑state buffers on its data lines
A single‑ended driver only
Open‑collector outputs only
No control signals
Explanation - Tri‑state buffers allow each source to drive the bus only when enabled, preventing contention.
Correct answer is: Tri‑state buffers on its data lines
Q.71 Which of the following best describes the term 'setup time' for a D flip‑flop used in a register?
The minimum time the data must be stable before the clock edge
The time required to clear the flip‑flop
The duration of the clock pulse
The time after the clock edge when data must remain stable
Explanation - Setup time ensures the flip‑flop samples correct data on the active clock transition.
Correct answer is: The minimum time the data must be stable before the clock edge
Q.72 How many distinct patterns can a 4‑bit register hold?
16
8
4
32
Explanation - 2⁴ = 16 possible binary combinations.
Correct answer is: 16
Q.73 Which type of register is primarily used in serial communication to convert parallel data to a serial stream?
Parallel‑in‑serial‑out (PISO) shift register
Serial‑in‑parallel‑out (SIPO) shift register
Ring counter
Johnson counter
Explanation - PISO loads parallel data and then shifts it out serially, suitable for UART transmission.
Correct answer is: Parallel‑in‑serial‑out (PISO) shift register
Q.74 A 4‑bit register is designed with a 'load' pin, a 'clear' pin, and a 'clock' pin. If both 'load' and 'clear' are asserted simultaneously on a rising clock edge, which operation takes precedence in most designs?
Clear (reset to 0) takes precedence
Load takes precedence
Both operations are performed simultaneously
The register becomes undefined
Explanation - Clear is usually designed as an overriding, asynchronous or higher‑priority control.
Correct answer is: Clear (reset to 0) takes precedence
Q.75 In a register file, what is the purpose of a 'write enable' (WE) signal?
To allow data to be written into the selected register on the next clock edge
To clear all registers
To shift data between registers
To generate the address lines
Explanation - WE activates the write operation for the addressed register during the clock transition.
Correct answer is: To allow data to be written into the selected register on the next clock edge
Q.76 A 4‑bit shift register is used as a simple delay line. If the input data sequence is 1,0,1,1, and the clock period is 10 ns, after how many nanoseconds will the last input bit appear at the serial output?
40 ns
30 ns
20 ns
10 ns
Explanation - Each bit shifts one position per clock; the fourth bit needs 4 × 10 ns = 40 ns to travel through all stages.
Correct answer is: 40 ns
Q.77 What is a 'bit‑slip' error in the context of shift registers?
An unintended shift of bits causing misalignment
A failure to clear the register
A power‑supply glitch
An overflow condition
Explanation - Bit‑slip occurs when the timing causes a bit to be lost or duplicated, misaligning data.
Correct answer is: An unintended shift of bits causing misalignment
Q.78 A 4‑bit register has a 'load' input, a 'shift left' input, and a 'shift right' input. Which control scheme ensures that only one operation occurs at a time?
Use a 2‑bit selector (00‑load, 01‑shift left, 10‑shift right, 11‑hold)
Allow all three inputs to be high simultaneously
Prioritize shift left over load and shift right
Ignore the selector and always load
Explanation - A selector ensures mutually exclusive operation modes.
Correct answer is: Use a 2‑bit selector (00‑load, 01‑shift left, 10‑shift right, 11‑hold)
Q.79 In a 4‑bit register, which binary number corresponds to the hexadecimal value 0xA?
1010
1100
1001
0110
Explanation - Hex A = decimal 10 = binary 1010.
Correct answer is: 1010
Q.80 A register that can be written to on both the rising and falling edges of the clock is known as:
Dual‑edge triggered register
Single‑edge register
Asynchronous register
Level‑triggered register
Explanation - Dual‑edge registers capture data on both transitions, effectively doubling data throughput.
Correct answer is: Dual‑edge triggered register
Q.81 What advantage does a 'pipeline' of registers provide in a CPU?
Allows overlapping execution of multiple instruction stages
Reduces the need for an ALU
Eliminates the clock signal
Provides infinite storage
Explanation - Pipelining uses registers between stages so each stage can work on a different instruction simultaneously.
Correct answer is: Allows overlapping execution of multiple instruction stages
Q.82 If a 4‑bit register has a 'hold' mode, what is the state of its outputs during this mode?
Outputs retain their previous values
Outputs become all zeros
Outputs toggle each clock cycle
Outputs become undefined
Explanation - Hold mode disables loading and shifting, so the register keeps its current content.
Correct answer is: Outputs retain their previous values
Q.83 In a synchronous 4‑bit register, what is the minimum number of clock cycles required to load a new word and then shift it left twice?
3
2
4
1
Explanation - One cycle to load, then two additional cycles for each shift, totaling three cycles.
Correct answer is: 3
Q.84 Which of the following is NOT a typical feature of a modern register file in a microprocessor?
Integrated cache memory
Dual‑port read capability
Write‑back capability
Clock gating for power saving
Explanation - Cache is separate from the register file; registers store immediate operands, not cache lines.
Correct answer is: Integrated cache memory
Q.85 What is the binary result of performing a bitwise NOT on the 4‑bit value 0101?
1010
0110
1101
0010
Explanation - Bitwise NOT flips each bit: 0→1, 1→0, giving 1010.
Correct answer is: 1010
Q.86 A 4‑bit register is implemented using edge‑triggered D flip‑flops with a propagation delay of 4 ns. What is the fastest possible clock frequency that guarantees correct operation?
250 MHz
125 MHz
500 MHz
62.5 MHz
Explanation - Maximum frequency = 1 / 4 ns = 250 MHz.
Correct answer is: 250 MHz
Q.87 In a 4‑bit shift register used as a serial‑in‑parallel‑out device, how many clock pulses are needed to completely fill the register with new serial data?
4
1
2
8
Explanation - Each clock pulse shifts one bit in; four pulses are required for a 4‑bit register.
Correct answer is: 4
Q.88 Which register in a CPU typically holds the address of the next instruction to be fetched?
Program Counter (PC)
Accumulator (ACC)
Instruction Register (IR)
Status Register (SR)
Explanation - The PC points to the memory location of the upcoming instruction.
Correct answer is: Program Counter (PC)
Q.89 A register that can be both loaded and cleared asynchronously is said to be:
Asynchronous‑clear, asynchronous‑load register
Synchronous‑clear, synchronous‑load register
Dual‑edge register
Ring counter
Explanation - Both clear and load act independently of the clock.
Correct answer is: Asynchronous‑clear, asynchronous‑load register
Q.90 If a 4‑bit register holds the value 0110 and a parallel load of 1011 is attempted while the clear line is asserted, what will be the register content after the next clock edge?
0000
1011
0110
1111
Explanation - Clear overrides load; the register is forced to zero.
Correct answer is: 0000
Q.91 What is the main reason for using a 'pipeline register' between stages of a processor pipeline?
To store intermediate results and synchronize stages
To increase the voltage of the signals
To convert serial data to parallel
To generate random numbers
Explanation - Pipeline registers latch data at each stage boundary, allowing each stage to operate on stable inputs.
Correct answer is: To store intermediate results and synchronize stages
Q.92 A 4‑bit register uses a 'serial‑in' line and a 'parallel‑out' bus. This configuration is known as:
Serial‑in‑parallel‑out (SIPO)
Parallel‑in‑serial‑out (PISO)
Universal shift register
Ring counter
Explanation - SIPO accumulates serial bits into a parallel word.
Correct answer is: Serial‑in‑parallel‑out (SIPO)
Q.93 In a register file, a 'read address' input selects which register's data to output. If the file has 32 registers, how many bits are needed for the read address?
5
4
6
8
Explanation - 2⁵ = 32, so five address bits are required.
Correct answer is: 5
Q.94 Which type of register can be used to implement a simple finite‑state machine (FSM) for sequence detection?
Shift register with feedback
Parallel‑load register only
Ring counter without feedback
Accumulator register
Explanation - Feedback enables the register to remember previous bits, suitable for detecting patterns.
Correct answer is: Shift register with feedback
Q.95 What is the binary representation of the decimal number 0 in a 4‑bit register?
0000
1111
1000
0101
Explanation - All bits low represents zero.
Correct answer is: 0000
Q.96 A 4‑bit register with an asynchronous preset and clear is asserted simultaneously. What is the resulting state?
All bits become 1 (preset overrides clear)
All bits become 0 (clear overrides preset)
The register enters an undefined state
The register holds its previous value
Explanation - Simultaneous asynchronous set and reset create a race condition; the result is unpredictable.
Correct answer is: The register enters an undefined state
Q.97 Which of the following best describes a 'register file'?
A collection of multiple registers with common read/write logic
A single large shift register
A memory module with random access
An arithmetic logic unit
Explanation - Register files organize many registers into a single block with shared control circuitry.
Correct answer is: A collection of multiple registers with common read/write logic
Q.98 If a 4‑bit register is clocked at 100 MHz, what is the time interval between two consecutive rising edges?
10 ns
5 ns
20 ns
1 ns
Explanation - Period = 1 / frequency = 1 / 100 MHz = 10 ns.
Correct answer is: 10 ns
Q.99 A register that can be written to on both the rising and falling edges of the clock provides:
Double the data throughput compared to single‑edge operation
Half the data throughput
No change in throughput
Increased power consumption without benefit
Explanation - Capturing data on both edges effectively doubles the data rate for the same clock frequency.
Correct answer is: Double the data throughput compared to single‑edge operation
Q.100 Which of the following registers is specifically used to hold the instruction currently being executed?
Instruction Register (IR)
Program Counter (PC)
Accumulator (ACC)
Status Register (SR)
Explanation - The IR stores the fetched instruction while the CPU decodes and executes it.
Correct answer is: Instruction Register (IR)
Q.101 In a 4‑bit universal shift register, which control input combination selects the 'hold' mode (no operation)?
S1=0, S0=0
S1=1, S0=1
S1=0, S0=1
S1=1, S0=0
Explanation - Standard encoding: 00 = hold, 01 = shift right, 10 = shift left, 11 = parallel load.
Correct answer is: S1=0, S0=0
Q.102 A 4‑bit register uses D flip‑flops with a setup time of 2 ns and a hold time of 1 ns. If the clock period is 6 ns, is the timing safe?
Yes, because the period exceeds setup + hold
No, because the period is too short
Yes, because hold time is irrelevant
No, because setup time must be zero
Explanation - Total required timing = 2 ns + 1 ns = 3 ns; 6 ns period satisfies the requirement.
Correct answer is: Yes, because the period exceeds setup + hold
Q.103 In a 4‑bit register, the binary pattern 1100 corresponds to which hexadecimal value?
C
A
6
3
Explanation - Binary 1100 = decimal 12 = hexadecimal C.
Correct answer is: C
Q.104 A register that can be accessed by both the CPU and a peripheral device without data corruption typically uses:
Dual‑port architecture with separate read/write ports
Single‑ended bus only
Open‑collector outputs only
Asynchronous clear only
Explanation - Dual‑port registers allow concurrent access, preventing contention.
Correct answer is: Dual‑port architecture with separate read/write ports
Q.105 Which of the following is NOT a typical operation mode of a universal shift register?
Parallel load
Shift left
Shift right
Rotate 90°
Explanation - Universal shift registers support load, shift left/right, and hold; rotation in 2‑D space is not applicable.
Correct answer is: Rotate 90°
Q.106 What is the primary difference between a 'ring counter' and a regular binary counter?
A ring counter cycles a single ‘1’ through the stages, while a binary counter counts in binary.
A ring counter uses JK flip‑flops, while a binary counter uses D flip‑flops.
A ring counter cannot be reset, while a binary counter can.
A ring counter operates asynchronously.
Explanation - Ring counters are one‑hot sequences; binary counters increment through binary values.
Correct answer is: A ring counter cycles a single ‘1’ through the stages, while a binary counter counts in binary.
Q.107 In a 4‑bit register, what is the result of performing a left shift on the value 1001, assuming a 0 is shifted in from the right?
0010
0100
1100
0001
Explanation - Shifting left discards MSB (1) and introduces 0 at LSB: 1001 → 0010.
Correct answer is: 0010
Q.108 A register file with 8 registers, each 8 bits wide, requires how many bits of storage in total (ignoring control circuitry)?
64 bits
8 bits
16 bits
128 bits
Explanation - 8 registers × 8 bits = 64 bits.
Correct answer is: 64 bits
Q.109 Which of the following best describes a 'tri‑state' output used on a register's data bus?
The output can be high, low, or high‑impedance, allowing multiple devices to share the bus.
It can drive three different voltage levels.
It can only output a logical 1.
It is used to increase power consumption.
Explanation - Tri‑state buffers enable bus sharing by disconnecting the driver when not in use.
Correct answer is: The output can be high, low, or high‑impedance, allowing multiple devices to share the bus.
Q.110 In a 4‑bit shift register, if the serial input is tied to the register's most‑significant output (Q₃), what type of register is formed?
A rotary (circular) shift register
A parallel‑load register
A universal shift register
A ring counter
Explanation - Feedback from MSB to serial input creates a circular shift where bits circulate indefinitely.
Correct answer is: A rotary (circular) shift register
Q.111 What is the binary representation of the decimal number 7 in a 4‑bit register?
0111
1110
0011
1101
Explanation - 7 = 4 + 2 + 1 → 0111.
Correct answer is: 0111
Q.112 A register that can be cleared asynchronously and loaded synchronously is said to have:
Asynchronous clear, synchronous load
Synchronous clear, asynchronous load
Dual‑edge operation
Ring counter behavior
Explanation - Clear works independent of the clock; load occurs on a clock edge.
Correct answer is: Asynchronous clear, synchronous load
Q.113 If a 4‑bit register receives the data pattern 0011 on its parallel inputs while the load signal is high, what will be the output after the next rising clock edge?
0011
0000
1111
1100
Explanation - Parallel load transfers the external data into the register on the active edge.
Correct answer is: 0011
Q.114 What is the main drawback of using a simple shift register as a storage element for random access memory?
Access time depends on the position of the data (sequential)
It consumes too much power
It cannot store more than one bit
It requires a large number of external pins
Explanation - Shift registers are serial; to reach a specific bit you must shift through preceding bits.
Correct answer is: Access time depends on the position of the data (sequential)
Q.115 In a universal shift register, which control line configuration typically selects the 'parallel load' operation?
S1=1, S0=1
S1=0, S0=0
S1=1, S0=0
S1=0, S0=1
Explanation - The encoding 11 is commonly assigned to parallel load.
Correct answer is: S1=1, S0=1
Q.116 A 4‑bit register is used to store the result of a 4‑bit addition. Which component must be present to detect overflow?
Carry‑out (or overflow) detection logic
A shift register
A ring counter
A decoder
Explanation - Overflow detection monitors the carry out of the most significant bit.
Correct answer is: Carry‑out (or overflow) detection logic
Q.117 What is the binary result of adding 0101 and 0011 in a 4‑bit register (ignore overflow)?
1000
0110
0100
1110
Explanation - 0101 (5) + 0011 (3) = 1000 (8).
Correct answer is: 1000
Q.118 A register with a 'preset' input forces all bits to:
Logic 1
Logic 0
Toggle state
High‑impedance
Explanation - Preset (or set) asynchronously drives each flip‑flop output high.
Correct answer is: Logic 1
Q.119 Which of the following is an example of a 'dual‑port' register?
A register file with two independent read/write ports
A register that can shift left and right simultaneously
A register with both clear and preset inputs
A shift register with serial in/out
Explanation - Dual‑port registers provide separate paths for concurrent accesses.
Correct answer is: A register file with two independent read/write ports
Q.120 In a 4‑bit shift register, after loading 1110 and performing one right shift with a 1 entering the MSB, what is the new content?
1111
0111
0110
1101
Explanation - Right shift moves bits toward LSB, inserts 1 at MSB: 1110 → 1111.
Correct answer is: 1111
Q.121 A 4‑bit register is part of a microcontroller's I/O port. Which feature allows the CPU to read the current state of external pins?
Input buffer (tri‑state) with read enable
Shift operation
Parallel load only
Serial‑in only
Explanation - The I/O port uses tri‑state buffers to isolate the pins when reading.
Correct answer is: Input buffer (tri‑state) with read enable
Q.122 What is the binary representation of the hexadecimal digit 'B' in a 4‑bit register?
1011
1100
1001
1110
Explanation - Hex B = decimal 11 = binary 1011.
Correct answer is: 1011
Q.123 If a 4‑bit register is clocked on the falling edge, which statement is true?
Data is captured when the clock transitions from high to low.
Data is captured when the clock transitions from low to high.
Data is captured continuously while the clock is low.
The register does not need a clock.
Explanation - Falling‑edge‑triggered devices respond to the high‑to‑low transition.
Correct answer is: Data is captured when the clock transitions from high to low.
Q.124 A register used to hold the address of a subroutine during a function call is typically called:
Link Register (LR)
Program Counter (PC)
Accumulator (ACC)
Status Register (SR)
Explanation - The LR stores the return address for subroutine calls.
Correct answer is: Link Register (LR)
Q.125 Which of the following statements about asynchronous and synchronous registers is correct?
Asynchronous controls act independently of the clock, while synchronous controls act on clock edges.
Synchronous registers do not require a clock.
Asynchronous registers are always faster than synchronous ones.
Synchronous registers cannot have a clear input.
Explanation - Asynchronous signals affect the register immediately; synchronous signals wait for a clock transition.
Correct answer is: Asynchronous controls act independently of the clock, while synchronous controls act on clock edges.
Q.126 In a 4‑bit universal shift register, which control inputs would you assert to perform a 'rotate left' operation (MSB wraps to LSB)?
Select shift left and connect serial input to Q₃
Select shift right and connect serial input to Q₀
Select parallel load with the same data
Select hold mode
Explanation - Rotating left feeds the MSB back into the serial input while shifting left.
Correct answer is: Select shift left and connect serial input to Q₃
Q.127 What is the primary function of the 'status register' in a CPU?
To hold condition flags such as zero, carry, overflow, and sign
To store program instructions
To act as the main arithmetic unit
To generate the system clock
Explanation - The status (or flag) register records the outcomes of operations for conditional branching.
Correct answer is: To hold condition flags such as zero, carry, overflow, and sign
Q.128 If a 4‑bit register is designed with an asynchronous clear and a synchronous load, and both are asserted together, which action will dominate?
Clear (reset) will dominate because it is asynchronous
Load will dominate because it is synchronous
Both actions will happen simultaneously, causing undefined state
Neither will happen; the register holds its previous value
Explanation - Asynchronous clear overrides synchronous load, forcing the register to zero immediately.
Correct answer is: Clear (reset) will dominate because it is asynchronous
Q.129 A 4‑bit shift register is used as a simple serial data transmitter. If the data to be sent is 1010, how many clock cycles are needed to transmit the entire word?
4
1
2
8
Explanation - One bit is transmitted per clock cycle; four bits need four cycles.
Correct answer is: 4
Q.130 Which register typically holds the operand address fetched from memory before the actual data is read?
Memory Address Register (MAR)
Accumulator (ACC)
Program Counter (PC)
Instruction Register (IR)
Explanation - The MAR stores the address of the memory location to be accessed.
Correct answer is: Memory Address Register (MAR)
Q.131 A 4‑bit universal shift register can be used to implement which of the following functions?
Parallel load, shift left, shift right, hold
Only parallel load
Only serial shift
Only rotation
Explanation - Universal shift registers are designed to support all four basic operations.
Correct answer is: Parallel load, shift left, shift right, hold
Q.132 What is the binary representation of the decimal number 12 in a 4‑bit register?
1100
1010
1001
0110
Explanation - 12 = 8 + 4 = binary 1100.
Correct answer is: 1100
Q.133 In a register file, why is a 'write mask' sometimes used?
To enable selective writing of particular bits within a register
To increase the clock speed
To clear all registers simultaneously
To shift data automatically
Explanation - A write mask allows only certain bits to be updated, leaving others unchanged.
Correct answer is: To enable selective writing of particular bits within a register
Q.134 If a 4‑bit register is clocked at 200 MHz, what is the clock period?
5 ns
10 ns
2 ns
20 ns
Explanation - Period = 1 / 200 MHz = 5 ns.
Correct answer is: 5 ns
Q.135 Which operation is performed by a 'parallel‑in‑serial‑out' (PISO) shift register?
Loads a parallel word and then shifts it out serially
Shifts data in serially and outputs parallel
Rotates data left
Acts as a ring counter
Explanation - PISO registers convert parallel data into a serial stream.
Correct answer is: Loads a parallel word and then shifts it out serially
Q.136 A 4‑bit register uses D flip‑flops with a propagation delay of 3 ns. What is the maximum clock frequency at which the register can operate reliably?
333 MHz
500 MHz
250 MHz
100 MHz
Explanation - Maximum frequency = 1 / 3 ns ≈ 333 MHz.
Correct answer is: 333 MHz
Q.137 In a universal shift register, what does the 'hold' mode do?
Keeps the current data unchanged
Shifts data left
Shifts data right
Loads new parallel data
Explanation - Hold mode disables both shifting and loading, preserving the register content.
Correct answer is: Keeps the current data unchanged
Q.138 Which of the following registers is most closely associated with interrupt handling?
Interrupt Vector Table Register (IVR)
Program Counter (PC)
Accumulator (ACC)
Status Register (SR)
Explanation - The IVR holds the address of the interrupt service routine to be executed.
Correct answer is: Interrupt Vector Table Register (IVR)
Q.139 A 4‑bit register is cleared asynchronously while a clock pulse is occurring. What is the expected output immediately after the clear signal is released (assuming no other inputs change)?
All bits remain at 0 until the next clock edge
Bits return to their previous values
Bits become undefined
Bits toggle randomly
Explanation - After asynchronous clear, the register stays cleared; without a load or shift, it holds zeros.
Correct answer is: All bits remain at 0 until the next clock edge
Q.140 Which of the following is a common use for a 'shift register' in digital communication?
Serial-to-parallel conversion for UART transmission
Generating high‑frequency clocks
Storing large files
Performing complex arithmetic
Explanation - Shift registers serialize or deserialize data streams in communication protocols.
Correct answer is: Serial-to-parallel conversion for UART transmission
Q.141 In a 4‑bit register, what is the result of performing a bitwise XOR between 1100 and 1010?
0110
1110
1000
0100
Explanation - XOR yields 1 when bits differ: 1⊕1=0, 1⊕0=1, 0⊕1=1, 0⊕0=0 → 0110.
Correct answer is: 0110
Q.142 A register file has 16 registers, each 32 bits wide. How many address lines are needed to select a specific register for reading?
4
5
8
16
Explanation - 2⁴ = 16, so four address bits are required.
Correct answer is: 4
Q.143 Which of the following best explains why registers are placed close to the CPU core?
To minimize latency and maximize data throughput
Because they require large physical space
To act as external memory
To provide power regulation
Explanation - Proximity reduces signal travel time, allowing faster access than off‑chip memory.
Correct answer is: To minimize latency and maximize data throughput
Q.144 If a 4‑bit register is loaded with the value 0011 and then a left shift is performed with a '1' entering the LSB, what is the new content?
0111
0010
0101
1010
Explanation - Shift left discards MSB (0), moves bits left, and inserts 1 at LSB: 0011 → 0111.
Correct answer is: 0111