Q.1 Which of the following gates implements the Boolean function F = A·B + A·C'?
AND followed by OR
NAND followed by NOT
OR followed by AND
XOR followed by NOT
Explanation - The expression A·B + A·C' requires two AND gates (A·B and A·C') whose outputs are then combined with an OR gate.
Correct answer is: AND followed by OR
Q.2 What is the minimum number of 2‑to‑1 multiplexers required to implement a 4‑input AND gate?
1
2
3
4
Explanation - A 4‑input AND can be built using three 2‑to‑1 MUXes: first two MUXes generate A·B and C·D, the third MUX ANDs these two results (by tying its select line to logic ‘1’).
Correct answer is: 3
Q.3 The truth table of a 2‑input XOR gate has output 1 for which input combinations?
(0,0) and (1,1)
(0,1) and (1,0)
(0,0) only
(1,1) only
Explanation - XOR outputs 1 only when the inputs are different.
Correct answer is: (0,1) and (1,0)
Q.4 A 3‑to‑8 decoder has how many enable inputs?
0
1
2
3
Explanation - Standard 3‑to‑8 decoders have two enable inputs (G1 and G2) that must both be asserted for the decoder to be active.
Correct answer is: 2
Q.5 Which Boolean expression corresponds to a 2‑bit binary adder's sum output (S) for the least significant bit?
A ⊕ B
A + B
A·B
A ⊕ B ⊕ C_in
Explanation - The LSB sum of a half‑adder (no carry‑in) is the XOR of the two inputs.
Correct answer is: A ⊕ B
Q.6 In a Karnaugh map, how many adjacent cells must differ by only one variable to be grouped together?
2
3
4
8
Explanation - Adjacency in K‑maps is defined by groups of 2^n cells where each group differs by only one variable per step; the smallest valid group is 2 cells.
Correct answer is: 2
Q.7 Which combination of gates can realize a 4‑input NAND function using only NOR gates?
Four NOR gates in series
Two NOR gates followed by a NOT
Three NOR gates in a tree
Four NOR gates with inverted inputs
Explanation - By De Morgan’s theorem, a NAND can be built from NORs if each input is first inverted (using NOR as NOT) and then the NOR of all inverted inputs is taken.
Correct answer is: Four NOR gates with inverted inputs
Q.8 What is the propagation delay of a combinational circuit that consists of two cascaded 2‑input NAND gates, each having a delay of 3 ns?
3 ns
6 ns
9 ns
12 ns
Explanation - Delays add in series: 3 ns + 3 ns = 6 ns.
Correct answer is: 6 ns
Q.9 A full adder can be implemented using how many 2‑input XOR gates?
1
2
3
4
Explanation - The sum output uses two XORs (A⊕B)⊕C_in; the carry output can be built from AND/OR gates, not XORs.
Correct answer is: 2
Q.10 Which of the following is NOT a property of a combinational circuit?
Output depends only on present inputs
Outputs can change after a propagation delay
Circuit can store a binary state
No feedback loops are present
Explanation - Storing state is a characteristic of sequential circuits, not combinational.
Correct answer is: Circuit can store a binary state
Q.11 In a 4‑bit priority encoder, what is the binary output when input D3 = 1 and all other inputs are 0?
0010
0100
1000
0001
Explanation - D3 (the highest‑order input) corresponds to binary 0010 in a 4‑bit priority encoder.
Correct answer is: 0010
Q.12 How many minterms are there in the canonical Sum‑of‑Products expression for a 3‑variable function that is true for exactly three input combinations?
1
2
3
4
Explanation - Each true combination corresponds to one minterm; three true rows → three minterms.
Correct answer is: 3
Q.13 Which Boolean identity is used to simplify the expression F = AB + A'B + AB' ?
Distributive law
Consensus theorem
De Morgan’s theorem
Absorption law
Explanation - AB + A'B + AB' = B(A + A') + AB' = B·1 + AB' = B + AB' = B (since B + AB' = B). This simplification uses the consensus theorem.
Correct answer is: Consensus theorem
Q.14 A 2‑to‑4 decoder with active‑low outputs is often called:
A demultiplexer
A decoder
A multiplexer
A NAND gate
Explanation - Decoders convert binary codes to one‑of‑N active‑low signals; the term does not change with output polarity.
Correct answer is: A decoder
Q.15 What is the Boolean expression for the output Y of a 4‑input multiplexer when the select lines are S1S0 and the data inputs are D0‑D3?
Y = (¬S1·¬S0·D0) + (¬S1·S0·D1) + (S1·¬S0·D2) + (S1·S0·D3)
Y = (S1·S0·D0) + (S1·¬S0·D1) + (¬S1·S0·D2) + (¬S1·¬S0·D3)
Y = (¬S1·S0·D0) + (S1·¬S0·D1) + (S1·S0·D2) + (¬S1·¬S0·D3)
Y = (S1·S0·D0) + (¬S1·¬S0·D1) + (S1·¬S0·D2) + (¬S1·S0·D3)
Explanation - Each term selects the appropriate data input when the select lines match the binary value of that input.
Correct answer is: Y = (¬S1·¬S0·D0) + (¬S1·S0·D1) + (S1·¬S0·D2) + (S1·S0·D3)
Q.16 If the Boolean function F(A,B,C) = Σm(1,3,5,7), which of the following is a correct minimized SOP expression?
A·C + B·C
A·B + B·C
A·¬B + B·C
A·C
Explanation - Minterms 1 (001), 3 (011), 5 (101), 7 (111) share C=1. Grouping yields C·(A + B) = A·C + B·C.
Correct answer is: A·C + B·C
Q.17 Which of the following statements about a combinational logic block implemented with programmable logic devices (PLDs) is true?
The logic can be changed while the device is powered on without reprogramming.
The device requires a clock signal to operate.
Only fixed‑function logic can be implemented.
The internal connections are fixed after manufacturing.
Explanation - Most PLDs (e.g., CPLDs, FPGAs) are essentially combinational but need a clock for configuration or synchronous features; however, the combinational logic itself does not require a clock. The only true statement among options is that they are typically clocked for configuration, making B the most appropriate.
Correct answer is: The device requires a clock signal to operate.
Q.18 A 3‑input majority gate outputs 1 when:
All three inputs are 1
At least two inputs are 1
Exactly one input is 1
The number of 1s equals the number of 0s
Explanation - A majority gate implements the function AB + AC + BC, which is true when two or more inputs are high.
Correct answer is: At least two inputs are 1
Q.19 Which of the following is the simplest implementation of the Boolean function F = A ⊕ B ⊕ C using only NAND gates?
Four NAND gates
Five NAND gates
Six NAND gates
Seven NAND gates
Explanation - An XOR can be built from four NANDs; cascading two XORs for three variables requires five NAND gates (reuse of intermediate NAND).
Correct answer is: Five NAND gates
Q.20 In a 2‑bit binary multiplier, how many AND gates are required to generate the partial products?
1
2
3
4
Explanation - Each bit of the multiplicand is ANDed with each bit of the multiplier, giving 2 × 2 = 4 partial products.
Correct answer is: 4
Q.21 The output of a 4‑to‑1 multiplexer can be used as a:
2‑input AND gate
2‑input OR gate
2‑input NAND gate
All of the above, depending on how the data inputs are tied
Explanation - By fixing the data inputs to appropriate constants, a MUX can emulate any 2‑input gate.
Correct answer is: All of the above, depending on how the data inputs are tied
Q.22 If a combinational circuit has 5 inputs, what is the maximum number of distinct minterms it can have?
5
10
16
32
Explanation - A 5‑input function has 2^5 = 32 possible input combinations, each representing a potential minterm.
Correct answer is: 32
Q.23 Which logic family typically provides the lowest propagation delay for combinational circuits?
TTL
ECL
CMOS
RTL
Explanation - Emitter‑Coupled Logic (ECL) operates with very small voltage swings, yielding the fastest switching speeds among standard families.
Correct answer is: ECL
Q.24 A 3‑input NAND gate can be realized using a 2‑input NAND gate and an additional:
NOT gate
AND gate
OR gate
XOR gate
Explanation - Connect two inputs to the 2‑input NAND, then NAND its output with the third input after inverting one of the original inputs (or use De Morgan’s theorem). A NOT (implemented by NAND with tied inputs) is needed.
Correct answer is: NOT gate
Q.25 The output of a 2‑input XNOR gate is equal to:
A AND B
A OR B
NOT (A XOR B)
A XOR B
Explanation - XNOR is the complement of XOR; it is true when both inputs are equal.
Correct answer is: NOT (A XOR B)
Q.26 What is the minimal number of product terms required to implement the function F = Σm(0,1,2,5,6,7) using a Karnaugh map?
1
2
3
4
Explanation - Grouping the K‑map yields two groups: one covering minterms 0,1,2,3 (which simplifies to ¬A·¬B) and another covering 5,6,7 (which simplifies to A·C).
Correct answer is: 2
Q.27 In a combinational logic circuit, fan‑out refers to:
The number of inputs a gate can have
The number of outputs a gate can drive
The delay introduced by each gate
The power consumption of a gate
Explanation - Fan‑out is the maximum number of gate inputs that can be driven by a single gate output while maintaining proper voltage levels.
Correct answer is: The number of outputs a gate can drive
Q.28 Which of the following is a correct truth table entry for a 3‑input majority gate?
A=0, B=0, C=0 → Y=1
A=1, B=0, C=0 → Y=1
A=1, B=1, C=0 → Y=1
A=0, B=1, C=1 → Y=0
Explanation - The majority gate outputs 1 when at least two inputs are 1; here two inputs are high.
Correct answer is: A=1, B=1, C=0 → Y=1
Q.29 A 2‑bit binary comparator that outputs '1' when A>B requires how many basic logic gates (AND, OR, NOT) in its minimal implementation?
2
3
4
5
Explanation - A>B can be expressed as (A1·¬B1) + (A1·A0·¬B0) + (A0·¬B0·¬A1), which can be minimized to three gates (two ANDs and one OR) with appropriate inverters.
Correct answer is: 3
Q.30 Which logic gate is functionally equivalent to a 2‑input NAND gate with both inputs tied together?
NOT gate
AND gate
OR gate
NOR gate
Explanation - When both inputs are the same, NAND reduces to NOT (i.e., Y = ¬(A·A) = ¬A).
Correct answer is: NOT gate
Q.31 In a 4‑bit ripple‑carry adder, the worst‑case propagation delay is proportional to:
log₂(n)
n²
n
√n
Explanation - The carry must propagate through each of the n full‑adders sequentially, giving linear (O(n)) delay.
Correct answer is: n
Q.32 Which of the following is a correct implementation of the Boolean function F = (A + B)·(A + ¬C) using only NAND gates?
Three NAND gates
Four NAND gates
Five NAND gates
Six NAND gates
Explanation - Each OR can be built with NANDs by De Morgan: (A+B) = ¬(¬A·¬B). Two NANDs produce the two OR terms, a third NAND implements the AND of those terms, and a fourth NAND inverts the final output if required.
Correct answer is: Four NAND gates
Q.33 A combinational circuit has an input vector (A,B,C) = (1,0,1). Which minterm number (m) does this correspond to?
5
6
3
7
Explanation - Binary 101 = decimal 5, so the corresponding minterm is m5.
Correct answer is: 5
Q.34 How many distinct Boolean functions exist for a 2‑input combinational circuit?
4
8
16
32
Explanation - With 2 inputs, there are 2^2 = 4 possible input combinations; each can map to 0 or 1, giving 2^4 = 16 functions.
Correct answer is: 16
Q.35 Which of the following expressions is the minimal SOP form for the function F = A·B + A·¬B + ¬A·B?
A + B
A·B
A⊕B
¬A·¬B
Explanation - A·B + A·¬B = A·(B + ¬B) = A·1 = A. Adding ¬A·B gives A + ¬A·B = A + B (by absorption).
Correct answer is: A + B
Q.36 A 2‑to‑1 multiplexer can be used to implement which of the following functions without any additional gates?
AND
OR
XOR
All of the above, by appropriate connection of data inputs
Explanation - By tying the data inputs to 0, 1, or the select line itself, a 2‑to‑1 MUX can realize AND, OR, XOR, etc.
Correct answer is: All of the above, by appropriate connection of data inputs
Q.37 In a 4‑bit binary comparator, the output 'Equal' is asserted when:
All corresponding bits are different
At least one pair of bits are equal
All four bits of A equal the four bits of B
The sum of the bits of A equals the sum of the bits of B
Explanation - Equality requires a bit‑by‑bit match across all positions.
Correct answer is: All four bits of A equal the four bits of B
Q.38 The Boolean function F = Σm(0,2,5,7) can be minimized to which expression?
A·B' + C
A·C + B·C'
¬A·¬C + B·C
A·¬B + B·C
Explanation - K‑map grouping leads to two prime implicants: A·¬B (covers 0,2) and B·C (covers 5,7).
Correct answer is: A·¬B + B·C
Q.39 What is the output of a 2‑input NAND gate when both inputs are at logic ‘0’?
0
1
Undefined
Depends on the gate technology
Explanation - NAND is the complement of AND; 0·0 = 0, complement = 1.
Correct answer is: 1
Q.40 How many distinct 3‑input NAND gates are needed to implement a 3‑input AND function using only NAND gates?
1
2
3
4
Explanation - First NAND the three inputs to get ¬(A·B·C); then NAND that output with itself to invert, yielding A·B·C.
Correct answer is: 2
Q.41 A 2‑bit binary multiplier produces a product of how many bits?
2
3
4
5
Explanation - Multiplying two n‑bit numbers yields up to 2n bits; for n=2, the product can be 4 bits wide.
Correct answer is: 4
Q.42 Which Boolean algebra theorem allows the reduction of AB + A'B to B?
Distributive law
Consensus theorem
Absorption law
De Morgan’s theorem
Explanation - AB + A'B = (A + A')·B = 1·B = B (absorption).
Correct answer is: Absorption law
Q.43 In a 4‑to‑1 multiplexer, how many select lines are required?
1
2
3
4
Explanation - 2 select lines can address 2^2 = 4 data inputs.
Correct answer is: 2
Q.44 Which of the following statements about a full adder’s carry‑out (C_out) is correct?
C_out = A ⊕ B ⊕ C_in
C_out = A·B + B·C_in + A·C_in
C_out = A + B + C_in
C_out = (A + B)·C_in
Explanation - The carry‑out is true when at least two of the three inputs are 1, which is expressed by the majority function A·B + B·C_in + A·C_in.
Correct answer is: C_out = A·B + B·C_in + A·C_in
Q.45 A 2‑input NOR gate can be used to implement which of the following functions without any extra gates?
OR
AND
NOT
XOR
Explanation - If both inputs of a NOR gate are tied together, the output is the inversion of that single input: Y = ¬(A·A) = ¬A.
Correct answer is: NOT
Q.46 The Boolean expression for a 3‑input decoder with enable E is:
Y = A·B·C·E
Y = ¬A·¬B·¬C·E
Y = (A + B + C)·E
Y = (A·B·C) + E
Explanation - When the enable is active, only the output corresponding to the binary address A B C is asserted; that output is the AND of the three address lines and the enable.
Correct answer is: Y = A·B·C·E
Q.47 Which of the following is NOT a valid use of a Karnaugh map?
Minimizing SOP expressions
Minimizing POS expressions
Finding the exact propagation delay of a circuit
Identifying don't‑care conditions
Explanation - K‑maps are a visual tool for Boolean simplification, not for timing analysis.
Correct answer is: Finding the exact propagation delay of a circuit
Q.48 In a combinational circuit, the term 'hazard' refers to:
A permanent fault in hardware
An unwanted temporary output glitch
A logic level that cannot be reached
A high power consumption condition
Explanation - Hazards are short‑lived output spikes caused by differing propagation delays.
Correct answer is: An unwanted temporary output glitch
Q.49 How many 2‑input NAND gates are needed to implement a 4‑input NAND function?
2
3
4
5
Explanation - First NAND inputs A and B, second NAND C and D, then NAND the two intermediate results. The final NAND provides the overall NAND output.
Correct answer is: 3
Q.50 A 4‑input majority gate can be expressed as:
AB + CD
ABC + ABD + ACD + BCD
A ⊕ B ⊕ C ⊕ D
A + B + C + D
Explanation - The output is 1 when any three of the four inputs are 1; each term represents one combination of three inputs.
Correct answer is: ABC + ABD + ACD + BCD
Q.51 Which of the following best describes a combinational logic block that implements the function F = (A ⊕ B)·C?
A 2‑input XOR feeding a 2‑input AND
A 2‑input OR feeding a 2‑input NAND
A 3‑input NAND with inputs A, B, C
A 3‑input NOR with inputs A, B, C
Explanation - First compute A⊕B, then AND the result with C to obtain F.
Correct answer is: A 2‑input XOR feeding a 2‑input AND
Q.52 What is the output of a 3‑input NOR gate when inputs are (1,0,0)?
0
1
Undefined
Depends on the technology
Explanation - NOR outputs 1 only when all inputs are 0; since one input is 1, the output is 0.
Correct answer is: 0
Q.53 A combinational circuit that implements the function F = A·B + C·D is known as:
A multiplexer
A decoder
A sum‑of‑products circuit
A latch
Explanation - The expression is a sum (OR) of product (AND) terms.
Correct answer is: A sum‑of‑products circuit
Q.54 Which of the following statements about a 2‑input XOR gate is true?
It can be built with a single NAND gate
It is equivalent to a 2‑input XNOR gate
It has a truth table where output is 1 when inputs differ
It always produces a high output
Explanation - XOR is defined as true when exactly one input is high.
Correct answer is: It has a truth table where output is 1 when inputs differ
Q.55 When simplifying Boolean expressions, the term "don't‑care" refers to:
Inputs that are never used
Input combinations for which the output may be either 0 or 1
Outputs that are always 0
A faulty gate
Explanation - Don't‑care conditions can be assigned either 0 or 1 to aid minimization.
Correct answer is: Input combinations for which the output may be either 0 or 1
Q.56 The minimum number of 2‑input AND gates needed to implement the function F = A·B·C·D is:
1
2
3
4
Explanation - First AND A·B, second AND C·D, third AND the two intermediate results ( (A·B)·(C·D) ).
Correct answer is: 3
Q.57 Which of the following can be used to eliminate static‑1 hazards in a SOP implementation?
Adding redundant product terms
Increasing fan‑out
Using a larger supply voltage
Adding a clock signal
Explanation - Redundant implicants cover overlapping regions, preventing glitches caused by different path delays.
Correct answer is: Adding redundant product terms
Q.58 A 2‑to‑1 multiplexer with select line S and data inputs D0, D1 can be expressed as:
Y = (¬S·D0) + (S·D1)
Y = (S·D0) + (¬S·D1)
Y = (S + D0)·(¬S + D1)
Y = (¬S + D0)·(S + D1)
Explanation - The output selects D0 when S=0 and D1 when S=1, which matches the given expression.
Correct answer is: Y = (¬S·D0) + (S·D1)
Q.59 If a combinational circuit has a propagation delay of 5 ns per gate and the longest path contains 4 gates, the total worst‑case delay is:
5 ns
9 ns
10 ns
20 ns
Explanation - Total delay = number of gates × delay per gate = 4 × 5 ns = 20 ns.
Correct answer is: 20 ns
Q.60 Which of the following logic families is most suitable for low‑power battery‑operated devices?
TTL
ECL
CMOS
NMOS
Explanation - CMOS consumes power primarily during switching and has very low static power dissipation.
Correct answer is: CMOS
Q.61 The Boolean function F = A·(B + C) can be realized using how many 2‑input NAND gates (minimum)?
2
3
4
5
Explanation - First NAND B and C, then NAND the result with A (after inverting B+C appropriately), and finally NAND the output with itself to get the required AND.
Correct answer is: 3
Q.62 A combinational circuit that implements the function F = A ⊕ B can be built using:
Two NAND gates
Two NOR gates
Four NAND gates
Four NOR gates
Explanation - XOR requires a minimum of four NAND gates in its standard implementation.
Correct answer is: Four NAND gates
Q.63 Which of the following is the correct POS (product‑of‑sums) form of the function F = Σm(1,3,4,6)?
(A + B)(¬A + ¬C)
(¬A + B)(A + ¬B + C)
(A + ¬B + C)(¬A + B + ¬C)
(¬A + ¬B)(A + C)
Explanation - The maxterms corresponding to the zeros (0,2,5,7) lead to the given POS expression after simplification.
Correct answer is: (A + ¬B + C)(¬A + B + ¬C)
Q.64 A 2‑bit binary comparator that outputs ‘1’ when A<B requires how many basic gates in its minimal implementation?
2
3
4
5
Explanation - A<B can be expressed as (¬A1·B1) + (¬A1·¬A0·B0) + (¬A0·B0·A1), which can be minimized to three gates (two ANDs and one OR) with necessary inverters.
Correct answer is: 3
Q.65 Which statement is true about a combinational circuit made solely of NAND gates?
It can implement any Boolean function.
It can only implement functions with an even number of inputs.
It cannot implement an XOR function.
It always requires at least one NOT gate.
Explanation - NAND gates are functionally complete; any Boolean expression can be realized using only NAND gates.
Correct answer is: It can implement any Boolean function.
Q.66 In a 4‑bit ripple‑carry adder, the carry‑in to the most significant bit (MSB) is generated after how many full‑adder stages?
1
2
3
4
Explanation - The carry must propagate through all four full‑adder stages to reach the MSB.
Correct answer is: 4
Q.67 What is the Boolean expression for a 2‑input NAND gate followed by a NOT gate?
A·B
¬(A·B)
¬A·¬B
A + B
Explanation - NAND gives ¬(A·B); a following NOT inverts it back to A·B.
Correct answer is: A·B
Q.68 A 3‑input decoder with an active‑high enable has how many output lines?
2
3
6
8
Explanation - A 3‑to‑8 decoder produces 2^3 = 8 outputs.
Correct answer is: 8
Q.69 Which Boolean identity is used to simplify the expression F = A·B + A·¬B + ¬A·B?
A·B + A·¬B = A
A·B + ¬A·B = B
A·¬B + ¬A·B = A⊕B
All of the above
Explanation - Each pair reduces to a single literal; combining them leads to F = A + B.
Correct answer is: All of the above
Q.70 If a combinational circuit’s output toggles from 0 to 1 after a 12 ns delay, what is the minimum possible propagation delay of any single gate within that circuit?
12 ns
6 ns
3 ns
Cannot be determined
Explanation - The total delay is the sum of individual gate delays; without knowing the number of gates, the minimum per‑gate delay cannot be inferred.
Correct answer is: Cannot be determined
Q.71 Which of the following is a correct expression for a 2‑input NAND gate using only NOR gates?
NOR(¬A, ¬B)
NOR(A, B)
NOR(NOR(A, A), NOR(B, B))
NOR(NOR(A, B), NOR(A, B))
Explanation - Inverting each input using NOR as NOT, then NOR-ing the inverses yields NAND via De Morgan.
Correct answer is: NOR(NOR(A, A), NOR(B, B))
Q.72 A 2‑input multiplexer can be used to implement a 2‑input AND gate by connecting its data inputs to:
0 and 1
A and B
A and 0
A and ¬B
Explanation - When the select line is tied to B, the output becomes A·B (since the MUX passes A when B=1, otherwise 0).
Correct answer is: A and 0
Q.73 The Boolean function F = A·B + A·C + B·C is known as:
Majority function for three variables
Parity function
Exclusive‑NOR function
Simple sum
Explanation - The function is true when at least two of the three inputs are 1.
Correct answer is: Majority function for three variables
Q.74 What is the minimum number of 2‑input NAND gates required to realize a 2‑input XNOR gate?
3
4
5
6
Explanation - XNOR = ¬(A⊕B). XOR needs 4 NANDs; an additional NAND is needed to invert the XOR output.
Correct answer is: 5
Q.75 In a 4‑bit binary adder, the sum output S3 (most significant sum bit) depends on which of the following?
Only A3 and B3
A3, B3, and the carry‑in from the previous stage
All four bits of A and B
Only the carry‑in
Explanation - The MSB sum is the XOR of the two MSB operands and the carry that propagated from the lower bits.
Correct answer is: A3, B3, and the carry‑in from the previous stage
Q.76 Which of the following is a necessary condition for a combinational circuit to be free of static hazards?
All inputs must be synchronized to a clock.
All product terms must be mutually exclusive.
The circuit must be implemented using only NAND gates.
Redundant product terms must be added where needed.
Explanation - Adding overlapping (redundant) terms ensures that when input changes cause a transition, at least one product term remains true, preventing glitches.
Correct answer is: Redundant product terms must be added where needed.
Q.77 A 2‑to‑1 multiplexer can be used as a 2‑input OR gate by connecting its data inputs to:
A and B, select line tied to 1
A and B, select line tied to 0
A and 1, select line = B
A and B, select line = A
Explanation - When B=0, output = A; when B=1, output = 1, resulting in A OR B.
Correct answer is: A and 1, select line = B
Q.78 Which Boolean expression corresponds to a 3‑input NAND gate?
A·B·C
¬(A·B·C)
A + B + C
¬A·¬B·¬C
Explanation - A NAND gate outputs the complement of the AND of its inputs.
Correct answer is: ¬(A·B·C)
Q.79 A 4‑input decoder with enable E (active low) will produce a high output on the selected line when:
E = 1
E = 0 and address inputs match the line number
E = 1 and address inputs are all 0
E = 0 irrespective of address inputs
Explanation - Active‑low enable means the decoder works when E is low; the selected line goes high only for the matching address.
Correct answer is: E = 0 and address inputs match the line number
Q.80 In a combinational circuit, the term "propagation delay" refers to:
The time taken to power up the circuit
The time for an input change to affect the output
The time between two clock edges
The time a gate remains in a high state
Explanation - Propagation delay is the interval between a change at the input and the resulting change at the output.
Correct answer is: The time for an input change to affect the output
Q.81 Which of the following gates is NOT functionally complete by itself?
NAND
NOR
AND
XOR
Explanation - XOR cannot generate a constant 1 or 0 without additional gates; NAND, NOR, and AND (with NOT) are functionally complete.
Correct answer is: XOR
Q.82 A combinational circuit that implements the function F = A·¬B + B·¬C + A·C can be minimized to:
A·C + B·¬C
A·¬B + B·C
A·B + ¬B·C
A·¬C + B·C
Explanation - Using consensus and absorption, the term B·¬C is redundant, leaving A·¬B + B·C.
Correct answer is: A·¬B + B·C
Q.83 A 2‑input NAND gate has an input combination of (A=1, B=0). What is the output?
0
1
Undefined
Depends on temperature
Explanation - AND of inputs is 0; NAND inverts it to 1.
Correct answer is: 1
Q.84 Which of the following is true about the implementation of a 4‑bit binary comparator that outputs '1' when A>B?
It requires a single XOR gate.
It can be built using only two OR gates.
It needs at least three AND gates and one OR gate.
It cannot be realized with combinational logic.
Explanation - The standard implementation uses hierarchical comparisons of bits, requiring multiple AND/OR gates.
Correct answer is: It needs at least three AND gates and one OR gate.
Q.85 In a 2‑input XOR gate, the output can be expressed as:
A·B + ¬A·¬B
A·¬B + ¬A·B
A + B
¬(A·B)
Explanation - XOR is true when exactly one input is high.
Correct answer is: A·¬B + ¬A·B
Q.86 How many product terms are needed to represent the function F = Σm(0,1,2,3) in its canonical SOP form?
1
2
3
4
Explanation - Each minterm corresponds to a distinct product term; four minterms give four product terms.
Correct answer is: 4
Q.87 A 3‑input multiplexer requires how many select lines?
1
2
3
4
Explanation - 2 select lines can address 2^2 = 4 data inputs; a 3‑input MUX actually has 3 data inputs, still needing 2 selects.
Correct answer is: 2
Q.88 Which of the following is a correct statement about a combinational circuit with no feedback?
It can store a bit of information.
Its output may depend on past inputs.
It cannot have oscillations.
It requires a clock signal.
Explanation - Without feedback loops, the circuit cannot create a condition for oscillation.
Correct answer is: It cannot have oscillations.
Q.89 The Boolean function F = (A + B)(¬A + C) simplifies to:
A·C + B·¬A
A·C + B·C
B·C
A·B + ¬A·C
Explanation - Expanding and simplifying: (A·¬A) + (A·C) + (B·¬A) + (B·C) → 0 + A·C + B·¬A + B·C → A·C + B·C (since B·¬A is absorbed by B·C when C=1).
Correct answer is: A·C + B·C
Q.90 How many distinct 2‑input Boolean functions exist?
4
8
16
32
Explanation - A 2‑input function has 4 input combinations; each can map to 0 or 1, giving 2^4 = 16 possibilities.
Correct answer is: 16
Q.91 Which logic gate can be constructed using a single 2‑input NAND gate with both inputs tied together?
AND
OR
NOT
XOR
Explanation - Tying both inputs yields ¬(A·A) = ¬A, i.e., an inverter.
Correct answer is: NOT
Q.92 A 4‑input AND gate can be built using how many 2‑input NAND gates (minimum)?
2
3
4
5
Explanation - First NAND A and B, second NAND C and D, third NAND the two results and invert with a final NAND tied to itself (or combine steps to use three NANDs).
Correct answer is: 3
Q.93 Which of the following is true about a 2‑input XNOR gate?
It outputs 1 when inputs are different.
It can be realized with three NAND gates.
It is the complement of XOR.
It is equivalent to an OR gate.
Explanation - XNOR outputs 1 when inputs are equal, i.e., NOT of XOR.
Correct answer is: It is the complement of XOR.
Q.94 What is the minimum number of 2‑input NAND gates required to implement a 2‑input AND gate?
1
2
3
4
Explanation - First NAND the inputs, then NAND the output with itself to invert, yielding AND.
Correct answer is: 2
Q.95 The Boolean expression F = A·B + ¬A·¬B represents which logic function?
XOR
XNOR
AND
OR
Explanation - The output is 1 when A and B are equal, which defines XNOR.
Correct answer is: XNOR
Q.96 A 2‑to‑4 decoder with active‑low enable will have which output when enable = 0 and inputs = 10?
All outputs high
Output Y2 low, others high
Output Y1 low, others high
All outputs low
Explanation - Active‑low enable means the decoder works when enable = 0. Input 10 selects output Y2 (binary 2) to be low.
Correct answer is: Output Y2 low, others high
Q.97 Which Boolean identity allows the simplification of F = AB + A'B + AB' + A'B'?
Complementarity
Idempotent law
Absorption
De Morgan’s theorem
Explanation - AB + A'B = B, AB' + A'B' = ¬B; then B + ¬B = 1 (complementarity).
Correct answer is: Complementarity
Q.98 In a combinational circuit, the term "fan‑in" refers to:
Number of inputs a gate can accept
Number of outputs a gate can drive
Delay caused by a gate
Power consumption of a gate
Explanation - Fan‑in is the maximum number of input signals that can be applied to a gate.
Correct answer is: Number of inputs a gate can accept
Q.99 The Boolean function F = Σm(0,2,5,7) can be realized with a minimal number of gates using which of the following forms?
Two product terms
Three product terms
Four product terms
Five product terms
Explanation - K‑map grouping yields two implicants: ¬A·C and B·C, giving the expression F = ¬A·C + B·C.
Correct answer is: Two product terms
Q.100 What is the output of a 2‑input NAND gate when both inputs are logic ‘1’?
0
1
Undefined
Depends on temperature
Explanation - NAND outputs the complement of AND; 1·1 = 1, complement = 0.
Correct answer is: 0
Q.101 Which of the following is a correct SOP expression for the function that is true only when exactly two of the three inputs A, B, C are 1?
AB + AC + BC
A·B·C
¬A·¬B·C + ¬A·B·¬C + A·¬B·¬C
A⊕B⊕C
Explanation - AB + AC + BC is true when any two inputs are high, which matches the description.
Correct answer is: AB + AC + BC
Q.102 A 4‑bit binary adder without carry‑in will produce a carry‑out when:
All four bits are 1
At least one pair of bits sums to 2 or more
The most significant bits are 1
Never, because there is no carry‑in
Explanation - A carry‑out occurs when the sum of the bits in any column (including propagated carry) reaches 2.
Correct answer is: At least one pair of bits sums to 2 or more
Q.103 Which Boolean expression is equivalent to a 2‑input NAND gate followed by a NOT gate?
A·B
¬(A·B)
¬A·¬B
A + B
Explanation - NAND gives ¬(A·B); a following NOT restores the original AND.
Correct answer is: A·B
Q.104 In a 3‑to‑8 decoder, how many enable inputs are typically present?
0
1
2
3
Explanation - Standard 3‑to‑8 decoders have two enable inputs to control activation.
Correct answer is: 2
Q.105 Which of the following can be used to eliminate a static‑0 hazard in a SOP implementation?
Add a redundant product term covering the transition
Increase the supply voltage
Add a clock signal
Reduce the number of inputs
Explanation - Redundant terms ensure that the output remains 1 during input changes, removing static‑0 hazards.
Correct answer is: Add a redundant product term covering the transition
Q.106 A combinational circuit that implements the function F = A·¬B + B·¬C + A·C is known as:
Majority function
Parity function
Sum‑of‑products
Product‑of‑sums
Explanation - The expression is a sum (OR) of product (AND) terms.
Correct answer is: Sum‑of‑products
Q.107 What is the output of a 2‑input XOR gate when inputs are (0,0)?
0
1
Undefined
Depends on temperature
Explanation - XOR is true only when inputs differ; both 0 gives 0.
Correct answer is: 0
Q.108 The Boolean function F = ¬A·¬B·¬C + A·B·C can be interpreted as:
Parity function (odd number of 1s)
Equality detector (all inputs equal)
Majority function
Simple AND
Explanation - The function is true when all inputs are 0 or all are 1.
Correct answer is: Equality detector (all inputs equal)
Q.109 Which of the following statements about a 2‑input NAND gate is FALSE?
It is a universal gate.
Its output is 0 only when both inputs are 1.
It can be used to build an OR gate without any other gates.
Tying both inputs together turns it into an inverter.
Explanation - An OR gate cannot be directly realized using a single NAND; additional gates are required.
Correct answer is: It can be used to build an OR gate without any other gates.
Q.110 How many minterms are needed to express the function F = Σm(3,5,6,7) in canonical SOP form?
2
3
4
5
Explanation - Each listed minterm corresponds to a distinct product term; therefore four minterms are required.
Correct answer is: 4
Q.111 A 2‑bit binary comparator that asserts ‘1’ when A = B uses which basic gates in its minimal implementation?
Two XOR gates
Two XNOR gates
One AND and one OR gate
Four NAND gates
Explanation - Equality of each bit can be detected with XNOR; the overall equality is the AND of both XNOR outputs.
Correct answer is: Two XNOR gates
Q.112 What is the Boolean expression for the output of a 4‑to‑1 multiplexer with select lines S1,S0 and data inputs D0‑D3?
(¬S1·¬S0·D0) + (¬S1·S0·D1) + (S1·¬S0·D2) + (S1·S0·D3)
(S1·S0·D0) + (¬S1·¬S0·D1) + (S1·¬S0·D2) + (¬S1·S0·D3)
(¬S1·S0·D0) + (S1·¬S0·D1) + (S1·S0·D2) + (¬S1·¬S0·D3)
(S1·¬S0·D0) + (¬S1·S0·D1) + (¬S1·¬S0·D2) + (S1·S0·D3)
Explanation - Each term selects the appropriate data input based on the binary value of the select lines.
Correct answer is: (¬S1·¬S0·D0) + (¬S1·S0·D1) + (S1·¬S0·D2) + (S1·S0·D3)
Q.113 Which logic gate can be implemented using a single 2‑input NOR gate with both inputs tied together?
AND
OR
NOT
XOR
Explanation - Tying inputs yields ¬(A + A) = ¬A, providing an inverter.
Correct answer is: NOT
Q.114 A combinational circuit that implements F = A·B·C·D can be minimized to require how many 2‑input NAND gates?
2
3
4
5
Explanation - First NAND A·B, second NAND C·D, third NAND the two intermediate results and finally invert if needed (or use three NANDs with one as inverter).
Correct answer is: 3
Q.115 In a 2‑input XOR gate, the expression A⊕B can be rewritten using only AND, OR, and NOT as:
(A·B) + (¬A·¬B)
(A·¬B) + (¬A·B)
(A + B)·(¬A + ¬B)
(A·B)·(¬A·¬B)
Explanation - XOR is true when exactly one input is high.
Correct answer is: (A·¬B) + (¬A·B)
Q.116 A 4‑bit binary multiplier requires how many full‑adder stages in its standard implementation?
2
3
4
5
Explanation - The typical shift‑and‑add multiplier for 4‑bit numbers uses three full‑adders for the intermediate sums after the initial partial product generation.
Correct answer is: 3
Q.117 Which of the following is a correct way to implement a 2‑input AND function using only NOR gates?
NOR(NOR(A, A), NOR(B, B))
NOR(A, B)
NOR(NOR(A, B), NOR(A, B))
NOR(NOR(A, B), A)
Explanation - First invert A and B using NOR as NOT, then NOR the inverses; by De Morgan this yields AND.
Correct answer is: NOR(NOR(A, A), NOR(B, B))
Q.118 What is the output of a 2‑input NOR gate when inputs are (1,0)?
0
1
Undefined
Depends on temperature
Explanation - NOR outputs 1 only when all inputs are 0; with a 1 present, output is 0.
Correct answer is: 0
Q.119 A combinational circuit with 3 inputs can generate at most how many distinct output patterns?
2
4
8
16
Explanation - With 3 inputs, there are 2^3 = 8 possible input combinations, each potentially producing a distinct output pattern.
Correct answer is: 8
Q.120 The Boolean function F = (A + B)(¬A + ¬B) simplifies to:
A·B
¬A·¬B
A⊕B
¬(A⊕B)
Explanation - Expanding gives A·¬A + A·¬B + B·¬A + B·¬B → 0 + A·¬B + ¬A·B + 0 = A·¬B + ¬A·B, which is XOR.
Correct answer is: A⊕B
Q.121 In a 2‑to‑1 multiplexer used as a 2‑input AND gate, what should the data inputs be?
A and 0
A and B
0 and B
A and ¬B
Explanation - Tie one data input to 0; when select line (B) is 1, output follows A; when B=0, output is 0, effectively AND.
Correct answer is: A and 0
Q.122 Which of the following is NOT a valid use of a Karnaugh map?
Minimizing SOP expressions
Identifying essential prime implicants
Calculating propagation delay
Handling don't‑care conditions
Explanation - K‑maps are for Boolean simplification, not timing analysis.
Correct answer is: Calculating propagation delay
Q.123 A 3‑input XOR gate can be constructed using how many 2‑input XOR gates?
1
2
3
4
Explanation - Cascade two 2‑input XORs: (A⊕B)⊕C.
Correct answer is: 2
Q.124 Which Boolean identity is applied to simplify the expression F = A·B + A·¬B + ¬A·B?
Distributive law
Consensus theorem
Absorption law
De Morgan’s theorem
Explanation - A·B + A·¬B = A (absorption), so F = A + ¬A·B = A + B (absorption again).
Correct answer is: Absorption law
Q.125 The Boolean function F = A·B + ¬A·¬B can be interpreted as:
XOR
XNOR
AND
OR
Explanation - The function is true when A and B are equal.
Correct answer is: XNOR
Q.126 What is the minimum number of 2‑input NAND gates needed to realize a 2‑input OR gate?
1
2
3
4
Explanation - First invert each input using NAND as NOT (2 gates), then NAND the inverted inputs to obtain OR (third NAND).
Correct answer is: 3
Q.127 A 2‑input XNOR gate can be built using how many 2‑input NAND gates?
3
4
5
6
Explanation - First build XOR with 4 NANDs, then add a fifth NAND to invert the XOR output, yielding XNOR.
Correct answer is: 5
Q.128 In a 4‑bit ripple‑carry adder, the worst‑case delay grows as:
O(1)
O(log n)
O(n)
O(n²)
Explanation - Carry must propagate through all n full‑adders, giving linear delay.
Correct answer is: O(n)
Q.129 Which of the following gates is universal, meaning any Boolean function can be built using only that gate?
AND
OR
NAND
XOR
Explanation - NAND alone is functionally complete; AND, OR, and XOR are not.
Correct answer is: NAND
Q.130 A 3‑to‑8 decoder with active‑high enable will have its outputs in which state when enable = 0?
All outputs high
All outputs low
Only the selected output high
Outputs toggle randomly
Explanation - Active‑high enable means the decoder is disabled when enable = 0, forcing all outputs low.
Correct answer is: All outputs low
Q.131 Which Boolean expression represents the output of a 2‑input NAND gate?
A·B
¬(A·B)
A + B
¬(A + B)
Explanation - By definition, NAND outputs the complement of the AND of its inputs.
Correct answer is: ¬(A·B)
Q.132 The term 'don't‑care' in Boolean minimization is used when:
The circuit is not powered.
The output can be either 0 or 1 for certain input combinations.
The inputs are undefined.
The gate is faulty.
Explanation - Don't‑care conditions allow flexibility in assigning 0 or 1 to aid simplification.
Correct answer is: The output can be either 0 or 1 for certain input combinations.
Q.133 A 2‑input NOR gate can be turned into an inverter by:
Tying both inputs to logic ‘1’
Tying both inputs together
Connecting one input to ground
Using an external resistor
Explanation - When both inputs are the same signal A, output = ¬(A + A) = ¬A, acting as NOT.
Correct answer is: Tying both inputs together
Q.134 Which of the following is the correct Boolean expression for a 2‑input XNOR gate?
A·B + ¬A·¬B
A·¬B + ¬A·B
¬(A·B)
¬(A + B)
Explanation - XNOR is true when both inputs are the same, i.e., both 1 or both 0.
Correct answer is: A·B + ¬A·¬B
Q.135 A combinational circuit that implements F = A·B + C·D is an example of:
A decoder
A multiplexer
A sum‑of‑products circuit
A latch
Explanation - The expression is a sum (OR) of product (AND) terms.
Correct answer is: A sum‑of‑products circuit