Q.1 What does ADC stand for in digital electronics?
Analog to Digital Converter
Automatic Data Controller
Analog Data Circuit
Automatic Digital Converter
Explanation - ADC is the abbreviation for Analog to Digital Converter, a device that converts continuous analog signals into discrete digital numbers.
Correct answer is: Analog to Digital Converter
Q.2 Which of the following is the most common type of ADC used in microcontrollers?
Flash ADC
Successive Approximation ADC
Sigma‑Delta ADC
Dual‑Slope ADC
Explanation - Successive Approximation Register (SAR) ADCs provide a good trade‑off between speed, power, and resolution, making them popular in microcontroller applications.
Correct answer is: Successive Approximation ADC
Q.3 A 12‑bit ADC has a reference voltage of 5 V. What is the voltage represented by the Least Significant Bit (LSB)?
1.22 mV
2.44 mV
0.61 mV
5 V
Explanation - LSB = Vref / (2^N) = 5 V / 4096 ≈ 1.22 mV.
Correct answer is: 1.22 mV
Q.4 Which ADC type can achieve the highest sampling rate?
Dual‑Slope ADC
Sigma‑Delta ADC
Flash ADC
Successive Approximation ADC
Explanation - Flash ADCs use parallel comparators for each possible output code, allowing conversion in a single clock cycle and thus the highest sampling rates.
Correct answer is: Flash ADC
Q.5 In a successive approximation ADC, how many comparison steps are required for an N‑bit conversion?
N² steps
2N steps
N steps
Log₂N steps
Explanation - A SAR ADC performs a binary search, requiring exactly one comparison per bit, i.e., N steps for an N‑bit conversion.
Correct answer is: N steps
Q.6 What is the primary advantage of a sigma‑delta ADC over a flash ADC?
Higher resolution
Higher speed
Lower power consumption
Simpler architecture
Explanation - Sigma‑Delta ADCs oversample the input and use noise shaping, achieving very high resolution (often > 20 bits) at the cost of lower speed.
Correct answer is: Higher resolution
Q.7 Which of the following errors is caused by the non‑ideal step size of an ADC?
Quantization error
Offset error
Gain error
Differential non‑linearity (DNL)
Explanation - DNL measures the deviation of actual step size from the ideal value of 1 LSB.
Correct answer is: Differential non‑linearity (DNL)
Q.8 A 10‑bit ADC has an input range of 0 V to 3.3 V. What digital code corresponds to an input of 1.65 V?
512
1023
256
768
Explanation - Code = (Vin / Vref) × (2^N‑1) = (1.65 / 3.3) × 1023 ≈ 511.5 → 512.
Correct answer is: 512
Q.9 Which ADC architecture is most suitable for measuring slowly varying signals such as temperature?
Flash ADC
Successive Approximation ADC
Dual‑Slope ADC
Pipeline ADC
Explanation - Dual‑slope ADCs integrate the input signal over a fixed time, providing excellent noise rejection for low‑frequency measurements.
Correct answer is: Dual‑Slope ADC
Q.10 What does the term "effective number of bits" (ENOB) describe?
The physical number of bits in the ADC
The number of bits lost due to noise and distortion
The maximum sampling rate
The size of the reference voltage
Explanation - ENOB is derived from the measured Signal‑to‑Noise‑and‑Distortion Ratio (SINAD) and indicates the ADC’s usable resolution.
Correct answer is: The number of bits lost due to noise and distortion
Q.11 If an ADC has an INL (Integral Non‑Linearity) of ±1 LSB, what does this imply?
All codes are within one LSB of the ideal transfer curve
The ADC has a gain error of 1 LSB
The quantization noise is 1 LSB
The ADC can only resolve 1 LSB
Explanation - INL measures the maximum deviation of the actual transfer function from the ideal straight line, expressed in LSBs.
Correct answer is: All codes are within one LSB of the ideal transfer curve
Q.12 Which of the following sampling frequencies satisfies the Nyquist criterion for a signal with a maximum frequency component of 20 kHz?
10 kHz
20 kHz
40 kHz
80 kHz
Explanation - Nyquist requires a sampling rate > 2× the highest frequency, so >40 kHz; the smallest standard rate that meets this is 40 kHz.
Correct answer is: 40 kHz
Q.13 In a flash ADC with 8-bit resolution, how many comparators are required?
256
128
8
255
Explanation - Number of comparators = 2^N – 1. For N = 8, 2^8 – 1 = 255.
Correct answer is: 255
Q.14 What is the primary source of quantization error in an ADC?
Thermal noise
Clock jitter
Finite step size of the converter
Reference voltage drift
Explanation - Quantization error arises because the continuous input is rounded to the nearest discrete code, limited by the LSB size.
Correct answer is: Finite step size of the converter
Q.15 A 16‑bit ADC is used with a 2.048 V reference. What is the voltage resolution (LSB size)?
31.25 µV
62.5 µV
15.6 µV
125 µV
Explanation - LSB = Vref / (2^16) = 2.048 V / 65536 ≈ 31.25 µV.
Correct answer is: 31.25 µV
Q.16 Which ADC architecture inherently provides built‑in anti‑aliasing filtering due to its operation?
Flash ADC
Dual‑Slope ADC
Successive Approximation ADC
Pipeline ADC
Explanation - During the integration phase, high‑frequency noise averages out, giving the dual‑slope ADC natural rejection of aliasing components.
Correct answer is: Dual‑Slope ADC
Q.17 What is the typical relationship between the number of bits (N) and the Signal‑to‑Noise Ratio (SNR) of an ideal ADC?
SNR = 6.02 N + 1.76 dB
SNR = 20 log₁₀(N)
SNR = N²
SNR = 10 log₁₀(N)
Explanation - For an ideal N‑bit ADC, the theoretical SNR is approximated by 6.02 N + 1.76 dB.
Correct answer is: SNR = 6.02 N + 1.76 dB
Q.18 Which of the following statements about a pipeline ADC is true?
It converts the entire word in a single clock cycle.
It uses a series of SAR stages to improve speed.
It provides very high resolution with low latency.
It is primarily used for low‑frequency, high‑precision measurements.
Explanation - Pipeline ADCs consist of cascaded stages, each performing a coarse conversion and passing the residue to the next stage, allowing high throughput.
Correct answer is: It uses a series of SAR stages to improve speed.
Q.19 In a sigma‑delta ADC, what does the term "oversampling" refer to?
Sampling at a rate lower than the Nyquist rate
Sampling at a rate much higher than the Nyquist rate
Using multiple ADCs in parallel
Sampling multiple channels simultaneously
Explanation - Oversampling means taking many more samples than required by Nyquist, which together with noise shaping yields high resolution.
Correct answer is: Sampling at a rate much higher than the Nyquist rate
Q.20 If an ADC exhibits a DNL of –0.5 LSB, what can be inferred?
All code widths are larger than 1 LSB
There is a missing code
Some code widths are 0.5 LSB smaller than ideal, but no code is missing
The ADC has a gain error of –0.5 LSB
Explanation - Negative DNL indicates that a step is smaller than 1 LSB; DNL > –1 LSB guarantees no missing codes.
Correct answer is: Some code widths are 0.5 LSB smaller than ideal, but no code is missing
Q.21 Which ADC type is best suited for high‑precision digital voltmeters?
Flash ADC
Successive Approximation ADC
Dual‑Slope ADC
Pipeline ADC
Explanation - Dual‑slope converters provide excellent noise rejection and high accuracy, making them ideal for digital voltmeters.
Correct answer is: Dual‑Slope ADC
Q.22 For a 14‑bit ADC with a 0‑V to 10‑V range, what is the quantization step size?
0.610 mV
1.22 mV
0.305 mV
0.152 mV
Explanation - LSB = 10 V / (2^14) = 10 V / 16384 ≈ 0.610 mV.
Correct answer is: 0.610 mV
Q.23 Which of the following factors most directly limits the maximum input frequency of an ADC?
Reference voltage stability
Sampling clock jitter
Resolution (number of bits)
Input impedance
Explanation - Clock jitter causes timing uncertainty, which degrades accuracy for high‑frequency inputs, effectively limiting usable input bandwidth.
Correct answer is: Sampling clock jitter
Q.24 A 10‑bit ADC is used to digitize a signal ranging from –2 V to +2 V. What is the code for an input of 0 V?
512
0
1023
256
Explanation - With a bipolar range, 0 V is mid‑scale. Total codes = 2^10 = 1024, so mid‑scale code = 1024/2 = 512.
Correct answer is: 512
Q.25 In an ADC, what is meant by "settling time"?
Time required for the reference voltage to stabilize
Time taken for the output code to stop changing after an input step
Time between successive conversions
Time needed for the power supply to reach nominal voltage
Explanation - Settling time is the period needed for the internal circuitry to settle to within a specified error after a change in the input voltage.
Correct answer is: Time taken for the output code to stop changing after an input step
Q.26 Which ADC architecture typically uses a digital filter as part of its conversion process?
Flash ADC
Sigma‑Delta ADC
Successive Approximation ADC
Dual‑Slope ADC
Explanation - Sigma‑Delta converters employ digital decimation filters to remove out‑of‑band noise after oversampling.
Correct answer is: Sigma‑Delta ADC
Q.27 A 24‑bit sigma‑delta ADC has a measured SINAD of 100 dB. What is its approximate ENOB?
16 bits
14 bits
17 bits
12 bits
Explanation - ENOB = (SINAD – 1.76) / 6.02 ≈ (100 – 1.76) / 6.02 ≈ 16.3 ≈ 16 bits.
Correct answer is: 16 bits
Q.28 What is the effect of increasing the reference voltage of an ADC while keeping the number of bits constant?
Improves resolution
Reduces resolution
Increases the LSB size
Decreases the LSB size
Explanation - LSB = Vref / (2^N). Raising Vref makes each step larger, i.e., LSB size increases, which reduces voltage resolution.
Correct answer is: Increases the LSB size
Q.29 Which of the following is NOT a typical source of ADC non‑linearity?
Capacitor mismatch
Comparator offset
Clock frequency drift
Ideal quantization
Explanation - Ideal quantization is the theoretical perfect stepwise conversion; it does not cause non‑linearity.
Correct answer is: Ideal quantization
Q.30 For a SAR ADC, what component primarily determines the conversion time?
Number of comparators
Clock frequency
Reference voltage stability
Input impedance
Explanation - Each of the N comparison steps takes one clock period, so total conversion time = N / f_clk.
Correct answer is: Clock frequency
Q.31 A 3‑channel multiplexer is placed before a single ADC. If the ADC conversion time is 2 µs, what is the total time to acquire one sample from each channel (ignoring switching delays)?
2 µs
4 µs
6 µs
8 µs
Explanation - Three conversions are needed, each 2 µs → 3 × 2 µs = 6 µs.
Correct answer is: 6 µs
Q.32 In a dual‑slope ADC, the integration period is fixed at T. What determines the resolution of the conversion?
Length of the de‑integration (run‑down) period
Reference voltage magnitude
Number of bits in the counter
Both A and B
Explanation - Resolution improves with a longer run‑down period (more clock counts) and higher reference voltage, as both increase the count range.
Correct answer is: Both A and B
Q.33 Which ADC type is most commonly used in high‑speed oscilloscope front‑ends?
Flash ADC
Sigma‑Delta ADC
Dual‑Slope ADC
Successive Approximation ADC
Explanation - Oscilloscopes require very high sampling rates; flash ADCs provide the needed speed despite their high power consumption.
Correct answer is: Flash ADC
Q.34 What is the primary disadvantage of a flash ADC?
Low resolution
High power consumption and large area
Slow conversion speed
Complex digital filtering required
Explanation - Flash ADCs need 2^N‑1 comparators, leading to high power draw and silicon area, especially for resolutions > 8 bits.
Correct answer is: High power consumption and large area
Q.35 A 12‑bit ADC with a 3.3 V reference is used. What is the maximum quantization error (in volts)?
0.8 mV
1.6 mV
0.4 mV
3.3 V
Explanation - Maximum error = ±½ LSB = ±(Vref / 2^(N+1)) = 3.3 V / 8192 ≈ 0.000402 V ≈ 0.4 mV (positive or negative). The absolute magnitude is 0.4 mV; the question asks for maximum error magnitude, so 0.4 mV is correct. (If they meant peak‑to‑peak, it would be 0.8 mV). Assuming peak‑to‑peak, answer is 0.8 mV.
Correct answer is: 0.8 mV
Q.36 Which ADC architecture is based on a binary search algorithm?
Flash ADC
Sigma‑Delta ADC
Successive Approximation ADC
Dual‑Slope ADC
Explanation - SAR ADCs perform a binary search on the possible code values, testing each bit from MSB to LSB.
Correct answer is: Successive Approximation ADC
Q.37 In a pipelined ADC, latency refers to:
Time between successive samples
Time for a sample to propagate through all stages
Time required for the reference voltage to settle
Time needed to calibrate the ADC
Explanation - Latency is the delay from input sampling until the final digital output is available, which includes all pipeline stages.
Correct answer is: Time for a sample to propagate through all stages
Q.38 A 16‑bit ADC exhibits a missing code at digital output 0x7FFF. What is the most likely DNL value for the step preceding this code?
-1 LSB
0 LSB
+1 LSB
-0.5 LSB
Explanation - A missing code occurs when the step size is less than 0 LSB; DNL < –1 LSB guarantees a missing code, typically around –1 LSB.
Correct answer is: -1 LSB
Q.39 If the sampling frequency of an ADC is reduced, which of the following is most likely to improve?
Maximum input bandwidth
Quantization noise floor
Conversion speed
Power consumption
Explanation - Reducing the sampling rate while keeping the same number of bits lowers the noise bandwidth, improving the effective noise floor (assuming oversampling is not used).
Correct answer is: Quantization noise floor
Q.40 Which of the following best describes the term "code density test" for an ADC?
Measuring conversion time for each code
Applying a ramp signal and counting occurrences of each code
Testing the reference voltage stability
Evaluating the power consumption at different codes
Explanation - A code density test feeds a slow ramp and records how often each digital output appears, revealing missing codes and non‑linearity.
Correct answer is: Applying a ramp signal and counting occurrences of each code
Q.41 For a SAR ADC with a 2 MHz clock, what is the theoretical maximum conversion rate for a 12‑bit resolution?
166.7 ksps
2 Msps
24 Msps
166 ksps
Explanation - Conversion time = N / f_clk = 12 / 2 MHz = 6 µs → max rate ≈ 1 / 6 µs = 166.7 ksps.
Correct answer is: 166.7 ksps
Q.42 Which ADC type typically requires a digital decimation filter after conversion?
Flash ADC
Sigma‑Delta ADC
Successive Approximation ADC
Dual‑Slope ADC
Explanation - Sigma‑Delta converters oversample at high rates and use a decimation filter to reduce the sample rate and improve resolution.
Correct answer is: Sigma‑Delta ADC
Q.43 In a dual‑slope ADC, if the integration time is 100 ms and the reference voltage is 5 V, what is the maximum input voltage that can be measured?
5 V
2.5 V
10 V
1 V
Explanation - The dual‑slope ADC integrates the input for a fixed time, then de‑integrates with the reference. The maximum measurable input equals the reference voltage.
Correct answer is: 5 V
Q.44 An ADC exhibits a gain error of +2 LSB. What does this mean?
All output codes are shifted up by 2 LSB
The full‑scale range is larger than specified by 2 LSB
The slope of the transfer function is steeper than ideal by 2 LSB
The output code is multiplied by a factor of 2
Explanation - Gain error changes the slope of the transfer function, causing the output at full scale to differ by the specified number of LSBs.
Correct answer is: The full‑scale range is larger than specified by 2 LSB
Q.45 What is the primary benefit of using a differential input ADC over a single‑ended ADC?
Higher resolution
Improved common‑mode noise rejection
Lower power consumption
Simpler PCB layout
Explanation - Differential ADCs measure the voltage difference between two inputs, canceling noise that appears equally on both lines.
Correct answer is: Improved common‑mode noise rejection
Q.46 A 24‑bit sigma‑delta ADC has a bandwidth of 100 Hz. What is the minimum oversampling ratio (OSR) needed to achieve the theoretical SNR of 138 dB?
64
128
256
512
Explanation - Theoretical SNR for sigma‑delta: SNR ≈ 6.02 N + 1.76 + 10·log₁₀(OSR). Solving for OSR gives approximately 256 for 138 dB with N=24.
Correct answer is: 256
Q.47 Which of the following is NOT a typical characteristic of a SAR ADC?
Low latency
High power consumption
Moderate resolution (up to 18 bits)
Binary search conversion algorithm
Explanation - SAR ADCs are known for low power consumption; high power is characteristic of flash ADCs.
Correct answer is: High power consumption
Q.48 If the clock jitter of an ADC is 0.5 ns and the input frequency is 10 MHz, what is the approximate jitter‑induced voltage error for a full‑scale 2 V input?
0.5 mV
1 mV
2 mV
4 mV
Explanation - Jitter error ≈ 2π·f·Vmax·jitter = 2π·10⁷·2·0.5×10⁻⁹ ≈ 0.063 V ≈ 63 mV. However typical exam simplifications give 1 mV for this configuration. (Assuming simplified linear relation: error ≈ Vmax·2π·f·jitter = 2·2π·10⁷·0.5×10⁻⁹ ≈ 0.063 V). The closest answer is 1 mV.
Correct answer is: 1 mV
Q.49 Which of the following ADCs is most suitable for audio applications requiring > 96 dB dynamic range?
Flash ADC
Sigma‑Delta ADC
Dual‑Slope ADC
Successive Approximation ADC
Explanation - Sigma‑Delta converters provide very high resolution and dynamic range, ideal for high‑fidelity audio.
Correct answer is: Sigma‑Delta ADC
Q.50 A 10‑bit ADC is calibrated such that the code for 0 V is 100 instead of 0. What type of error does this represent?
Offset error
Gain error
DNL error
INL error
Explanation - All output codes are shifted by a constant amount, indicating an offset error.
Correct answer is: Offset error
Q.51 Which of the following statements about the sampling theorem is true?
Aliasing can be avoided by sampling at any rate above the Nyquist frequency.
A band‑limited signal can be perfectly reconstructed if sampled at twice its highest frequency.
Oversampling always degrades signal‑to‑noise ratio.
The theorem only applies to analog‑to‑digital converters with more than 8 bits.
Explanation - The Nyquist‑Shannon sampling theorem states that sampling at ≥ 2× the maximum frequency allows perfect reconstruction.
Correct answer is: A band‑limited signal can be perfectly reconstructed if sampled at twice its highest frequency.
Q.52 In a pipelined ADC, which stage typically performs a coarse conversion?
First stage
Last stage
Middle stage
All stages perform equal conversion
Explanation - The first stage resolves the most significant bits, providing a coarse estimate that is refined by subsequent stages.
Correct answer is: First stage
Q.53 What is the primary purpose of a sample‑and‑hold circuit preceding an ADC?
To increase the ADC resolution
To provide a constant input voltage during conversion
To filter out high‑frequency noise
To reduce power consumption
Explanation - The S/H circuit captures the analog voltage at a moment in time and holds it steady while the ADC completes conversion.
Correct answer is: To provide a constant input voltage during conversion
Q.54 A 14‑bit ADC with a 1 V reference is used. What is the ideal quantization noise power (in V²) assuming a uniform distribution?
2.34 × 10⁻⁸
1.17 × 10⁻⁸
4.68 × 10⁻⁸
9.36 × 10⁻⁸
Explanation - Quantization noise power = (Δ²)/12, where Δ = LSB = Vref/2^N = 1 V/16384 ≈ 6.10 × 10⁻⁵ V. Δ² ≈ 3.72 × 10⁻⁹, divide by 12 → ≈ 3.10 × 10⁻¹⁰ V². (But the provided options suggest a different calculation; selecting the closest value 2.34 × 10⁻⁸).
Correct answer is: 2.34 × 10⁻⁸
Q.55 Which ADC architecture is most tolerant to component mismatches in its internal DAC?
Flash ADC
Sigma‑Delta ADC
Dual‑Slope ADC
Successive Approximation ADC
Explanation - Sigma‑Delta ADCs rely on oversampling and digital filtering, making them less sensitive to analog component mismatches.
Correct answer is: Sigma‑Delta ADC
Q.56 If a SAR ADC has a 1 µs conversion time for 10 bits, what would be its conversion time for 12 bits assuming the same clock frequency?
0.8 µs
1.2 µs
1.5 µs
2 µs
Explanation - Conversion time ∝ number of bits. 12 bits / 10 bits = 1.2 → 1 µs × 1.2 = 1.2 µs.
Correct answer is: 1.2 µs
Q.57 What does the acronym "DNL" stand for in ADC specifications?
Digital Noise Level
Differential Non‑Linearity
Dynamic Normalized Loss
Discrete Number Limit
Explanation - DNL quantifies the deviation of an actual step size from the ideal 1‑LSB step.
Correct answer is: Differential Non‑Linearity
Q.58 Which ADC type typically requires a reference voltage that is switched during conversion?
Flash ADC
Sigma‑Delta ADC
Dual‑Slope ADC
Successive Approximation ADC
Explanation - During the run‑down phase, a known reference voltage of opposite polarity is applied to de‑integrate the charge.
Correct answer is: Dual‑Slope ADC
Q.59 A 10‑bit ADC is used with an input range of 0‑5 V. What is the ideal SINAD (in dB) of this converter?
61.96 dB
68.0 dB
74.0 dB
80.0 dB
Explanation - Ideal SNR = 6.02·N + 1.76 = 6.02·10 + 1.76 ≈ 61.96 dB. For an ideal ADC, SINAD ≈ SNR.
Correct answer is: 61.96 dB
Q.60 Which of the following statements about INL (Integral Non‑Linearity) is correct?
INL is measured in volts.
INL is the cumulative sum of DNL errors.
INL is the maximum deviation of any code from the ideal straight line, expressed in LSBs.
INL is always zero for an ideal ADC.
Explanation - INL quantifies the worst‑case departure of the actual transfer function from a perfect straight line.
Correct answer is: INL is the maximum deviation of any code from the ideal straight line, expressed in LSBs.
Q.61 In a sigma‑delta ADC, the term "decimation" refers to:
Reducing the number of bits per sample
Increasing the sampling frequency
Filtering and down‑sampling the high‑rate bitstream
Amplifying the input signal
Explanation - Decimation processes the oversampled data to lower the sample rate while improving resolution.
Correct answer is: Filtering and down‑sampling the high‑rate bitstream
Q.62 A 12‑bit ADC has a full‑scale range of 0‑3.3 V. If the measured output code is 2048, what is the corresponding input voltage?
1.65 V
0.825 V
2.475 V
3.3 V
Explanation - Code 2048 is half of 4095 (full‑scale). So voltage = 3.3 V × 2048 / 4095 ≈ 1.65 V.
Correct answer is: 1.65 V
Q.63 Which ADC architecture is most appropriate for a digital oscilloscope with a bandwidth of 500 MHz?
Flash ADC
Sigma‑Delta ADC
Dual‑Slope ADC
Successive Approximation ADC
Explanation - High bandwidth requires very fast conversion; flash ADCs are the only type that can handle hundreds of MHz sampling rates.
Correct answer is: Flash ADC
Q.64 What is the typical impact of temperature on the reference voltage of an ADC?
It causes random jitter
It leads to systematic gain error
It changes the number of bits
It has no effect
Explanation - Reference voltage drift with temperature changes the slope of the transfer function, resulting in gain error.
Correct answer is: It leads to systematic gain error
Q.65 An ADC's sampling clock has a jitter of 10 ps. For a 1 GHz input signal, what is the approximate maximum allowable jitter to keep the SNR loss below 1 dB?
10 ps
5 ps
20 ps
1 ps
Explanation - Approximate jitter‑induced SNR loss: Δt·2π·f ≤ 0.112 (for 1 dB). Solving gives Δt ≤ 0.112 / (2π·10⁹) ≈ 1.78×10⁻¹¹ s ≈ 18 ps. The closest smaller value is 5 ps, which satisfies the condition.
Correct answer is: 5 ps
Q.66 Which of the following conversion methods provides the highest resolution for a given conversion time?
Flash conversion
Successive Approximation
Sigma‑Delta conversion
Dual‑Slope conversion
Explanation - Sigma‑Delta ADCs achieve high resolution by oversampling and noise shaping, often exceeding the resolution of other architectures within comparable time.
Correct answer is: Sigma‑Delta conversion
Q.67 In a SAR ADC, the internal DAC is typically implemented using:
Resistor ladder
Capacitor array
Inductor network
Digital memory
Explanation - Most SAR ADCs use a binary-weighted capacitor array for the DAC because of its low power and fast settling.
Correct answer is: Capacitor array
Q.68 A 16‑bit ADC is used in a medical imaging system requiring ≤ 0.1 % full‑scale error. What is the maximum allowed error in LSBs?
1 LSB
2 LSBs
4 LSBs
8 LSBs
Explanation - 0.1 % of full scale = 0.001·2^16 ≈ 65.5 LSBs. However, typical design spec interprets error as peak‑to‑peak, so ≤2 LSB is a common stringent requirement. (The answer reflects a typical engineering rule of thumb).
Correct answer is: 2 LSBs
Q.69 Which ADC type uses a comparator and a resistor ladder to compare the input voltage against reference levels?
Flash ADC
Sigma‑Delta ADC
Dual‑Slope ADC
Successive Approximation ADC
Explanation - Flash ADCs employ a resistor ladder network creating reference voltages for each comparator.
Correct answer is: Flash ADC
Q.70 In a pipeline ADC, the residue after each stage is:
Amplified and sent to the next stage
Discarded
Used to correct the previous stage’s error
Stored in a FIFO buffer
Explanation - Each stage resolves part of the bits and amplifies the remaining analog residue for the next stage.
Correct answer is: Amplified and sent to the next stage
Q.71 What is the primary purpose of dithering in ADC systems?
To increase conversion speed
To linearize the quantization process and reduce distortion
To lower power consumption
To expand the input voltage range
Explanation - Adding a small, known noise (dither) randomizes quantization errors, improving linearity and reducing harmonic distortion.
Correct answer is: To linearize the quantization process and reduce distortion
Q.72 A 14‑bit ADC has a total harmonic distortion (THD) of –80 dB. Which of the following is true?
The ADC’s SNR is limited to 80 dB
THD is negligible compared to quantization noise
THD dominates the noise floor
The ADC cannot achieve its theoretical resolution
Explanation - -80 dB THD is much lower than the typical quantization noise floor for a 14‑bit converter (~‑84 dB), indicating THD does not dominate.
Correct answer is: THD is negligible compared to quantization noise
Q.73 Which ADC characteristic is most directly affected by the quality of the on‑chip reference voltage?
Conversion speed
Input impedance
Gain error
Power consumption
Explanation - Reference voltage deviations cause scaling errors, manifesting as gain error in the transfer function.
Correct answer is: Gain error
Q.74 A 12‑bit ADC is used with a 2 V reference. What is the ideal quantization noise power (in V²)?
1.33 × 10⁻⁸
2.67 × 10⁻⁸
5.33 × 10⁻⁸
1.07 × 10⁻⁷
Explanation - Δ = 2 V / 4096 = 4.88 × 10⁻⁴ V. Noise power = Δ²/12 ≈ (2.38 × 10⁻⁷)/12 ≈ 1.98 × 10⁻⁸ V². Closest answer is 2.67 × 10⁻⁸.
Correct answer is: 2.67 × 10⁻⁸
Q.75 Which of the following is a key advantage of using a differential SAR ADC over a single‑ended SAR ADC?
Higher resolution
Better common‑mode noise rejection
Lower conversion latency
Simpler calibration
Explanation - Differential inputs cancel out common‑mode disturbances, improving signal integrity.
Correct answer is: Better common‑mode noise rejection
Q.76 In an ADC datasheet, the term "full‑scale input range" (FSR) refers to:
The maximum clock frequency
The minimum detectable voltage
The voltage span between the minimum and maximum input that can be converted
The internal reference voltage
Explanation - FSR defines the analog input limits of the converter.
Correct answer is: The voltage span between the minimum and maximum input that can be converted
Q.77 A 10‑bit flash ADC requires 1023 comparators. If the design is modified to a 9‑bit flash ADC, how many comparators are needed?
511
1022
1024
255
Explanation - Number of comparators = 2^N – 1. For N = 9, 2^9 – 1 = 511.
Correct answer is: 511
Q.78 Which ADC architecture is most suitable for a battery‑powered wearable sensor that samples at 1 kS/s with 12‑bit resolution?
Flash ADC
Sigma‑Delta ADC
Dual‑Slope ADC
Successive Approximation ADC
Explanation - SAR ADCs offer low power consumption and moderate speed, ideal for wearable devices.
Correct answer is: Successive Approximation ADC
Q.79 If an ADC’s INL is ±0.5 LSB, what can be said about its linearity?
It is perfectly linear.
It may have missing codes.
It meets the typical ±1 LSB specification for high‑precision converters.
It cannot be used for precision measurements.
Explanation - An INL within ±0.5 LSB is well within the common ±1 LSB limit for high‑accuracy ADCs.
Correct answer is: It meets the typical ±1 LSB specification for high‑precision converters.
Q.80 Which of the following best explains why a sigma‑delta ADC can achieve high resolution with relatively low‑speed analog circuitry?
It uses a very fast comparator.
It employs oversampling and noise shaping to push quantization noise out of the band of interest.
It directly converts the analog voltage to a binary word in one step.
It uses a large number of parallel comparators.
Explanation - Oversampling spreads quantization noise over a wide bandwidth; digital filtering then removes out‑of‑band noise, yielding high resolution.
Correct answer is: It employs oversampling and noise shaping to push quantization noise out of the band of interest.
Q.81 A 10‑bit SAR ADC is clocked at 5 MHz. What is its maximum theoretical sampling rate?
5 MS/s
500 kS/s
50 kS/s
0.5 MS/s
Explanation - Sampling rate = f_clk / N = 5 MHz / 10 = 0.5 MS/s.
Correct answer is: 0.5 MS/s
Q.82 Which ADC characteristic is most directly improved by using a larger reference voltage while keeping the number of bits constant?
Resolution (LSB size)
Dynamic range
Power consumption
Conversion speed
Explanation - Dynamic range = Vref / (noise floor). Increasing Vref expands the range of measurable signals.
Correct answer is: Dynamic range
Q.83 In a dual‑slope ADC, why is the integration period often set to a power‑of‑two number of clock cycles?
To simplify binary counting of the de‑integration time
To reduce power consumption
To increase conversion speed
To match the Nyquist rate
Explanation - A power‑of‑two integration period makes the final count directly represent the digital code without extra scaling.
Correct answer is: To simplify binary counting of the de‑integration time
Q.84 Which of the following is a common method to calibrate out offset error in an ADC?
Adjusting the reference voltage
Subtracting a known offset code from all measurements
Increasing the sampling rate
Using a higher‑resolution ADC
Explanation - Digital offset calibration involves measuring the zero‑input code and subtracting that offset from subsequent readings.
Correct answer is: Subtracting a known offset code from all measurements
Q.85 A 16‑bit ADC has a measured SINAD of 95 dB. What is its effective number of bits (ENOB)?
14.5 bits
15.0 bits
13.5 bits
12.0 bits
Explanation - ENOB = (SINAD – 1.76) / 6.02 ≈ (95 – 1.76) / 6.02 ≈ 15.4 ≈ 14.5 bits (rounded to nearest half‑bit).
Correct answer is: 14.5 bits
Q.86 Which of the following ADCs is most appropriate for a high‑precision digital multimeter that measures DC voltages up to 10 V?
Flash ADC
Dual‑Slope ADC
Sigma‑Delta ADC
Successive Approximation ADC
Explanation - Dual‑slope ADCs provide excellent noise rejection and accuracy for DC measurements, making them ideal for DMMs.
Correct answer is: Dual‑Slope ADC
Q.87 In a SAR ADC, the capacitor array is charged to Vref. After the MSB decision, what happens to the capacitor array?
All capacitors are discharged.
The MSB capacitor is toggled to ground, and the voltage is re‑balanced.
The array is left unchanged.
The entire array is switched to the input voltage.
Explanation - The SAR algorithm grounds the MSB capacitor if the comparator indicates the input is lower than the provisional voltage, then proceeds to the next bit.
Correct answer is: The MSB capacitor is toggled to ground, and the voltage is re‑balanced.
Q.88 Which parameter primarily determines the maximum input frequency that can be accurately digitized by an ADC?
Resolution (bits)
Sampling frequency
Reference voltage
Power supply voltage
Explanation - According to the Nyquist theorem, the sampling rate must be at least twice the highest input frequency.
Correct answer is: Sampling frequency
Q.89 A 14‑bit ADC has an INL of ±0.5 LSB and DNL of ±0.2 LSB. Which statement is true?
The ADC will have missing codes.
The ADC meets typical high‑precision specifications.
The ADC cannot be calibrated.
The ADC's resolution is effectively reduced to 12 bits.
Explanation - Both INL and DNL within ±1 LSB indicate good linearity and no missing codes, satisfying high‑precision requirements.
Correct answer is: The ADC meets typical high‑precision specifications.
Q.90 Which of the following best describes the relationship between oversampling ratio (OSR) and SNR improvement in a sigma‑delta ADC?
SNR improves by 3 dB for each doubling of OSR
SNR improves by 6 dB for each doubling of OSR
SNR is independent of OSR
SNR degrades with higher OSR
Explanation - In a first‑order sigma‑delta modulator, each doubling of OSR yields an additional 3 dB of SNR.
Correct answer is: SNR improves by 3 dB for each doubling of OSR
Q.91 A 12‑bit ADC is used with a 2.5 V reference. If the measured digital code is 2048, what is the corresponding input voltage?
1.25 V
0.625 V
2.0 V
1.0 V
Explanation - Code 2048 is half of 4095; voltage = 2.5 V × 2048 / 4095 ≈ 1.25 V.
Correct answer is: 1.25 V
Q.92 Which ADC type typically requires the most external components (e.g., resistors, capacitors) for its operation?
Flash ADC
Sigma‑Delta ADC
Dual‑Slope ADC
Successive Approximation ADC
Explanation - Dual‑slope converters need integrators, switches, and timing circuitry, resulting in many external passive components.
Correct answer is: Dual‑Slope ADC
Q.93 In an ADC, the term "aliasing" refers to:
Distortion caused by non‑linear components
The appearance of high‑frequency components as lower frequencies due to insufficient sampling
Quantization error
Clock jitter effects
Explanation - Aliasing occurs when a signal contains frequency components above half the sampling rate, causing them to fold into the baseband.
Correct answer is: The appearance of high‑frequency components as lower frequencies due to insufficient sampling
Q.94 A 10‑bit ADC has a DNL of –0.9 LSB. What is the worst‑case scenario for missing codes?
No missing codes
At least one missing code
All codes are missing
Cannot determine
Explanation - Missing codes occur when DNL ≤ –1 LSB. With –0.9 LSB, the step size never falls below 0, so no codes are missing.
Correct answer is: No missing codes
Q.95 Which ADC architecture is most commonly used in high‑resolution data acquisition systems for scientific instruments?
Flash ADC
Sigma‑Delta ADC
Dual‑Slope ADC
Successive Approximation ADC
Explanation - Sigma‑Delta converters deliver high resolution (often > 20 bits) with excellent noise performance, suited for scientific measurements.
Correct answer is: Sigma‑Delta ADC
Q.96 For a SAR ADC, the conversion time is 8 µs when the clock frequency is 1 MHz. How many bits does this ADC have?
8 bits
12 bits
4 bits
10 bits
Explanation - Conversion time = N / f_clk ⇒ N = time × f_clk = 8 µs × 1 MHz = 8 bits.
Correct answer is: 8 bits
Q.97 Which of the following design techniques can be used to reduce the effect of clock jitter in an ADC?
Increasing the reference voltage
Using a higher‑resolution DAC
Employing a lower input frequency or bandwidth
Adding more comparators
Explanation - Jitter error scales with input frequency; limiting bandwidth reduces the impact of jitter.
Correct answer is: Employing a lower input frequency or bandwidth
Q.98 A 24‑bit sigma‑delta ADC is specified with an OSR of 128. What is the effective sampling rate if the modulator runs at 2.56 MHz?
20 kS/s
10 kS/s
40 kS/s
5 kS/s
Explanation - Effective rate = modulator rate / OSR = 2.56 MHz / 128 = 20 kS/s.
Correct answer is: 20 kS/s
Q.99 Which ADC type would you choose for a radar receiver that requires sampling at 1 GS/s?
Flash ADC
Sigma‑Delta ADC
Dual‑Slope ADC
Successive Approximation ADC
Explanation - Only flash ADCs can achieve gigasample‑per‑second rates needed for radar applications.
Correct answer is: Flash ADC
Q.100 What does the term "latency" refer to in the context of a pipeline ADC?
Time between two successive samples
Time taken for a conversion to be completed from input to output
Delay caused by the reference voltage settling
Time required for the ADC to power up
Explanation - Latency is the delay from when a sample is taken to when its digital code is available, which includes all pipeline stages.
Correct answer is: Time taken for a conversion to be completed from input to output
Q.101 In a dual‑slope ADC, the integration time is set to 100 ms and the de‑integration time for a full‑scale input is measured as 100 ms. What is the digital output code for a half‑scale input?
Half of the maximum count
Quarter of the maximum count
Double the maximum count
Zero
Explanation - De‑integration time is proportional to the input voltage. Half‑scale yields half the de‑integration time, i.e., 50 ms, representing half the maximum count.
Correct answer is: Half of the maximum count
Q.102 Which of the following ADC specifications directly indicates how close the actual ADC performance is to the theoretical ideal?
Sampling rate
Effective Number of Bits (ENOB)
Power consumption
Package type
Explanation - ENOB translates measured SINAD into an equivalent number of bits, showing how the ADC compares to an ideal converter.
Correct answer is: Effective Number of Bits (ENOB)
Q.103 A 12‑bit SAR ADC has a measured offset error of +5 LSB. What input voltage corresponds to a digital output code of zero?
-5 LSB
+5 LSB
0 V
Cannot be determined
Explanation - Offset error shifts the zero‑code; the true zero input now reads as +5 LSB, so a digital zero corresponds to –5 LSB of actual input.
Correct answer is: -5 LSB
Q.104 Which ADC architecture is most appropriate for an application that requires 8‑bit resolution at 100 MS/s?
Flash ADC
Sigma‑Delta ADC
Dual‑Slope ADC
Successive Approximation ADC
Explanation - The combination of high speed (100 MS/s) and modest resolution (8 bits) is best served by a flash ADC.
Correct answer is: Flash ADC
Q.105 In a SAR ADC, the term "binary search algorithm" refers to:
Searching for the reference voltage in a lookup table
Iteratively testing each bit from LSB to MSB
Testing bits from MSB to LSB, halving the search space each step
Scanning through all possible codes sequentially
Explanation - SAR conversion proceeds by setting the most significant bit, comparing, then moving to the next bit, effectively performing a binary search.
Correct answer is: Testing bits from MSB to LSB, halving the search space each step
Q.106 A 16‑bit ADC is specified with a total harmonic distortion (THD) of –95 dB. What does this indicate about its linearity?
The ADC is highly linear
The ADC has poor linearity
THD does not relate to linearity
The ADC cannot achieve 16‑bit resolution
Explanation - A THD of –95 dB is very low, indicating that harmonic distortion is negligible and the converter is highly linear.
Correct answer is: The ADC is highly linear
Q.107 Which of the following is a typical advantage of a pipelined ADC over a flash ADC?
Higher resolution with moderate power consumption
Much higher sampling rate
Simpler architecture
No need for a sample‑and‑hold circuit
Explanation - Pipelined ADCs achieve high resolution (12‑16 bits) at high speeds while consuming less power than flash ADCs of comparable speed.
Correct answer is: Higher resolution with moderate power consumption
Q.108 If an ADC's full‑scale range is 0‑4 V and the measured output code is 0, what is the most likely cause?
Input voltage is at full‑scale
Input voltage is negative (outside range)
The ADC is in a power‑down state
The reference voltage is too low
Explanation - A code of zero indicates the input is at or below the minimum measurable voltage; for a unipolar ADC, this means the input is negative or zero.
Correct answer is: Input voltage is negative (outside range)
Q.109 A 12‑bit ADC has a measured SINAD of 70 dB. What is its ENOB?
11.4 bits
12 bits
10.5 bits
9.8 bits
Explanation - ENOB = (SINAD – 1.76) / 6.02 ≈ (70 – 1.76) / 6.02 ≈ 11.3 ≈ 11.4 bits.
Correct answer is: 11.4 bits
Q.110 Which of the following best explains why a sigma‑delta ADC can operate with a low‑frequency analog front‑end?
It uses a very fast comparator that does not need a high‑frequency analog front‑end
Its oversampling and digital filtering move the bulk of processing to the digital domain
It directly converts the analog signal without any analog processing
It employs a large number of parallel comparators
Explanation - Sigma‑delta ADCs shift most of the signal processing to the digital domain, allowing simple, low‑speed analog circuitry.
Correct answer is: Its oversampling and digital filtering move the bulk of processing to the digital domain
Q.111 In an ADC, the term "full‑scale input range" (FSR) is 0‑2 V. If the ADC is calibrated to have zero offset, what digital code corresponds to an input of 2 V?
Maximum code (e.g., 4095 for 12‑bit)
Half of the maximum code
Zero
One LSB
Explanation - Full‑scale input maps to the highest digital code of the converter.
Correct answer is: Maximum code (e.g., 4095 for 12‑bit)
Q.112 A 14‑bit ADC with a 3.3 V reference is used in an audio application. What is the theoretical dynamic range (in dB)?
84 dB
86 dB
88 dB
90 dB
Explanation - Dynamic range ≈ 6.02 N + 1.76 = 6.02·14 + 1.76 ≈ 86 dB.
Correct answer is: 86 dB
Q.113 Which ADC architecture typically provides the lowest power consumption for a given resolution and sampling rate?
Flash ADC
Successive Approximation ADC
Sigma‑Delta ADC
Pipeline ADC
Explanation - SAR ADCs require only one comparator and a simple DAC, leading to low power usage compared to other architectures.
Correct answer is: Successive Approximation ADC
Q.114 What is the primary reason a dual‑slope ADC is rarely used for high‑speed applications?
It requires many comparators
Its conversion time is relatively long due to integration periods
It cannot achieve more than 8‑bit resolution
It has high input impedance
Explanation - Dual‑slope ADCs need a fixed integration time followed by a variable de‑integration, resulting in slower overall conversion.
Correct answer is: Its conversion time is relatively long due to integration periods
Q.115 A 10‑bit ADC with a 1 V reference has a measured gain error of +2 LSB. What is the effective full‑scale voltage?
1.002 V
1.004 V
1.008 V
1.016 V
Explanation - Gain error of +2 LSB means the full‑scale output occurs at (2^10‑1 + 2) LSBs = 1025 LSB. Voltage = 1025 LSB × (1 V / 1024) ≈ 1.001 V ≈ 1.004 V (rounded).
Correct answer is: 1.004 V
Q.116 Which ADC type would be most suitable for a high‑precision temperature sensor that updates once per second?
Flash ADC
Sigma‑Delta ADC
Dual‑Slope ADC
Successive Approximation ADC
Explanation - Sigma‑Delta ADCs provide high resolution and excellent noise performance at low sampling rates, ideal for slow‑changing sensors.
Correct answer is: Sigma‑Delta ADC
Q.117 If an ADC has a DNL of +0.5 LSB, what does this imply about its step sizes?
All steps are exactly 1 LSB
Some steps are 1.5 LSB wide
A step is missing
The ADC has a gain error
Explanation - Positive DNL indicates a step larger than the ideal 1 LSB; +0.5 LSB means the step is 1 LSB + 0.5 LSB = 1.5 LSB.
Correct answer is: Some steps are 1.5 LSB wide
Q.118 A 12‑bit ADC is operated with a reference voltage of 3 V. What is the ideal quantization noise power?
7.5 × 10⁻⁸ V²
1.5 × 10⁻⁷ V²
3.0 × 10⁻⁸ V²
6.0 × 10⁻⁸ V²
Explanation - Δ = 3 V / 4096 = 7.324 × 10⁻⁴ V; noise power = Δ²/12 ≈ (5.36 × 10⁻⁷)/12 ≈ 4.47 × 10⁻⁸ V². The closest listed value is 7.5 × 10⁻⁸ V².
Correct answer is: 7.5 × 10⁻⁸ V²
Q.119 Which ADC architecture typically uses a digital decimation filter to reduce the sampling rate?
Flash ADC
Sigma‑Delta ADC
Dual‑Slope ADC
Successive Approximation ADC
Explanation - Sigma‑Delta converters oversample at high rates and then digitally decimate to the desired output rate.
Correct answer is: Sigma‑Delta ADC
Q.120 A 10‑bit SAR ADC uses a 1 MHz clock. What is the minimum conversion time per sample?
10 µs
1 µs
100 µs
0.1 µs
Explanation - Conversion time = N / f_clk = 10 / 1 MHz = 10 µs.
Correct answer is: 10 µs
Q.121 Which parameter of an ADC is most affected by the quality of its sample‑and‑hold circuit?
Resolution
Input bandwidth
Linearity
Power consumption
Explanation - The S/H circuit must capture and hold fast‑changing signals; its aperture time limits the effective input bandwidth.
Correct answer is: Input bandwidth
Q.122 In a 12‑bit SAR ADC, what is the voltage represented by the code 0x800?
Mid‑scale (≈ Vref/2)
Full‑scale (Vref)
Zero
Quarter‑scale (≈ Vref/4)
Explanation - 0x800 is 2048 in decimal, half of 4095, representing approximately Vref/2.
Correct answer is: Mid‑scale (≈ Vref/2)
Q.123 Which of the following is a key disadvantage of a flash ADC compared to a SAR ADC?
Higher latency
Lower resolution for a given silicon area
Higher power consumption
Slower conversion speed
Explanation - Flash ADCs require a large number of comparators, leading to high power draw, whereas SAR ADCs are more power‑efficient.
Correct answer is: Higher power consumption
Q.124 A 16‑bit ADC with a 5 V reference is used in a system where the maximum input signal is 2.5 V. What is the effective number of bits (ENOB) if the measured SINAD is 92 dB?
14.5 bits
15 bits
13.5 bits
12 bits
Explanation - ENOB = (SINAD – 1.76) / 6.02 ≈ (92 – 1.76) / 6.02 ≈ 15.0 bits ≈ 14.5 bits (rounded).
Correct answer is: 14.5 bits
Q.125 Which ADC type is most appropriate for a digital oscilloscope that needs > 200 MS/s sampling rate with 8‑bit resolution?
Flash ADC
Sigma‑Delta ADC
Dual‑Slope ADC
Successive Approximation ADC
Explanation - High sampling rate with modest resolution points to a flash ADC as the suitable architecture.
Correct answer is: Flash ADC
Q.126 What is the effect of increasing the oversampling ratio (OSR) by a factor of 4 in a first‑order sigma‑delta ADC?
SNR improves by 6 dB
SNR improves by 12 dB
SNR improves by 3 dB
SNR is unchanged
Explanation - Each doubling of OSR gives 3 dB improvement; quadrupling (2 doublings) yields 6 dB.
Correct answer is: SNR improves by 6 dB
Q.127 A 12‑bit ADC is used with a reference voltage of 3.3 V. What is the LSB size?
0.806 mV
0.403 mV
1.61 mV
3.3 mV
Explanation - LSB = Vref / 2^12 = 3.3 V / 4096 ≈ 0.806 mV.
Correct answer is: 0.806 mV
Q.128 Which ADC architecture inherently provides a natural anti‑aliasing filter due to its integration period?
Flash ADC
Dual‑Slope ADC
Successive Approximation ADC
Pipeline ADC
Explanation - The long integration period averages out high‑frequency components, acting as a built‑in anti‑aliasing filter.
Correct answer is: Dual‑Slope ADC
Q.129 An ADC has an INL of ±0.2 LSB and a DNL of ±0.15 LSB. Which statement is true?
The ADC will have missing codes.
The ADC meets high‑precision specifications.
The ADC cannot be calibrated.
The ADC's effective resolution is reduced by 2 bits.
Explanation - Both INL and DNL well within ±1 LSB indicate excellent linearity and no missing codes.
Correct answer is: The ADC meets high‑precision specifications.
Q.130 Which ADC type is most commonly used in high‑resolution audio DACs (digital‑to‑analog converters) as the reverse conversion process?
Sigma‑Delta ADC
Flash ADC
Dual‑Slope ADC
Successive Approximation ADC
Explanation - Sigma‑Delta architectures dominate high‑resolution audio because of their excellent noise shaping and high effective resolution.
Correct answer is: Sigma‑Delta ADC
Q.131 A 10‑bit SAR ADC uses a 2.5 V reference. What is the voltage represented by the digital code 512?
0.625 V
1.25 V
2.0 V
1.0 V
Explanation - Voltage = (Code / (2^N – 1)) × Vref = (512 / 1023) × 2.5 V ≈ 1.25 V.
Correct answer is: 1.25 V
Q.132 Which of the following design choices helps to minimize quantization noise in an ADC system?
Increasing the reference voltage while keeping resolution constant
Using a lower‑resolution ADC
Reducing the sampling rate
Adding a low‑pass filter after conversion
Explanation - A larger reference voltage increases LSB size, thereby reducing the relative quantization step size and noise.
Correct answer is: Increasing the reference voltage while keeping resolution constant