Q.1 What does RISC stand for in computer architecture?
Reduced Instruction Set Computer
Random Instruction Set Computer
Rapid Instruction System Compiler
Recursive Instruction Set Code
Explanation - RISC stands for Reduced Instruction Set Computer, emphasizing a small set of simple instructions to improve performance.
Correct answer is: Reduced Instruction Set Computer
Q.2 Which is a primary characteristic of CISC architecture?
Complex instructions
Simple instructions
Uniform instruction length
Single-cycle execution for all instructions
Explanation - CISC (Complex Instruction Set Computer) uses complex instructions that can execute multiple low-level operations in one instruction.
Correct answer is: Complex instructions
Q.3 RISC processors typically require ____ clock cycles per instruction.
Many
One
Variable
Zero
Explanation - RISC architectures are designed so that most instructions execute in a single clock cycle, enabling faster execution.
Correct answer is: One
Q.4 Which of the following is an example of a CISC processor?
Intel x86
ARM Cortex-A
MIPS
SPARC
Explanation - Intel x86 is a classic example of a CISC processor, with a complex set of instructions capable of multiple operations per instruction.
Correct answer is: Intel x86
Q.5 Which architecture usually has a larger number of instructions?
CISC
RISC
Both equal
None
Explanation - CISC architectures have a larger number of instructions to reduce the number of instructions per program.
Correct answer is: CISC
Q.6 RISC processors generally require ____ memory for program storage compared to CISC.
More
Less
Equal
Variable
Explanation - Because RISC uses simple instructions, programs may require more instructions and thus more memory.
Correct answer is: More
Q.7 Which of the following is a typical feature of RISC architecture?
Fewer addressing modes
Complex addressing modes
Microcode execution
One instruction for multiple tasks
Explanation - RISC architectures simplify the processor design with fewer addressing modes and instructions.
Correct answer is: Fewer addressing modes
Q.8 In CISC architecture, an instruction can perform ____ operation(s).
Multiple
Single
Zero
Variable, but only arithmetic
Explanation - CISC instructions can perform multiple low-level operations like memory access, arithmetic, and control in a single instruction.
Correct answer is: Multiple
Q.9 Which architecture is more suitable for pipelining?
RISC
CISC
Both equally
Neither
Explanation - RISC instructions are simple and uniform in length, making them ideal for pipelining and faster execution.
Correct answer is: RISC
Q.10 Microcode is commonly associated with which architecture?
CISC
RISC
Both
Neither
Explanation - CISC processors often use microcode to implement complex instructions, translating them into simpler internal operations.
Correct answer is: CISC
Q.11 Which of the following reduces the instruction cycle time?
RISC
CISC
Both equally
None
Explanation - RISC designs use simple instructions and aim for one instruction per clock cycle, reducing the instruction cycle time.
Correct answer is: RISC
Q.12 CISC architecture aims to ____ the number of instructions per program.
Reduce
Increase
Keep constant
Eliminate
Explanation - CISC uses complex instructions to perform multiple tasks, reducing the total number of instructions needed for a program.
Correct answer is: Reduce
Q.13 Which architecture typically has simpler hardware design?
RISC
CISC
Both equal
None
Explanation - RISC simplifies hardware by having fewer and simpler instructions, fewer addressing modes, and uniform instruction formats.
Correct answer is: RISC
Q.14 Which architecture generally results in higher code density?
CISC
RISC
Both equal
None
Explanation - CISC instructions can perform more work per instruction, reducing program size and increasing code density.
Correct answer is: CISC
Q.15 Load/store architecture is a feature of ____.
RISC
CISC
Both
None
Explanation - RISC uses load/store architecture where operations occur between registers, and memory is accessed only via load/store instructions.
Correct answer is: RISC
Q.16 Which of the following is true regarding instruction length?
RISC instructions are usually fixed length
CISC instructions are usually fixed length
Both have variable length
Both have fixed length
Explanation - RISC instructions are typically of fixed length to simplify instruction decoding and enable pipelining.
Correct answer is: RISC instructions are usually fixed length
Q.17 Which architecture generally requires more complex compilers?
RISC
CISC
Both equally
Neither
Explanation - RISC processors rely on compilers to efficiently schedule simple instructions to achieve performance comparable to CISC.
Correct answer is: RISC
Q.18 Instruction pipelining is more efficient in ____ architectures.
RISC
CISC
Both equally
Neither
Explanation - Uniform and simple RISC instructions are easier to pipeline than complex and variable-length CISC instructions.
Correct answer is: RISC
Q.19 Which architecture was historically designed to minimize the number of instructions in a program?
CISC
RISC
Both equally
Neither
Explanation - CISC aims to reduce the total number of instructions, making programs shorter and easier to code with fewer instructions.
Correct answer is: CISC
Q.20 Which of the following is generally easier to optimize in hardware?
RISC
CISC
Both equally
Neither
Explanation - RISC’s simple and uniform instructions make hardware implementation and optimization easier.
Correct answer is: RISC
Q.21 Which of the following uses a higher-level language-like instruction set?
CISC
RISC
Both equally
Neither
Explanation - CISC instructions are designed to perform high-level operations similar to statements in high-level programming languages.
Correct answer is: CISC
Q.22 Which type of instruction format is simpler and easier to decode?
RISC
CISC
Both equally
None
Explanation - RISC instruction formats are simple and fixed, allowing faster decoding in the CPU.
Correct answer is: RISC
Q.23 Which of the following is an example of a RISC processor?
ARM Cortex-M
Intel Pentium
VAX
Motorola 68000
Explanation - ARM Cortex-M is a RISC processor designed with a simplified instruction set for efficient pipelining and performance.
Correct answer is: ARM Cortex-M
Q.24 CISC architectures often have ____ addressing modes.
More
Fewer
None
Variable but fixed per instruction
Explanation - CISC processors include a variety of addressing modes to simplify programming and support complex instructions.
Correct answer is: More
Q.25 RISC and CISC differ mainly in ____.
Instruction set complexity
Clock speed
Cache size
Number of cores
Explanation - The key difference is the complexity of the instruction set: RISC has simple instructions, CISC has complex instructions.
Correct answer is: Instruction set complexity