Q.1 What is the main purpose of instruction pipelining in a CPU?
To reduce the clock speed of the processor
To execute multiple instructions simultaneously
To increase the instruction execution latency
To reduce the size of the instruction set
Explanation - Pipelining allows overlapping the execution of instructions, increasing throughput by executing multiple instructions at different stages simultaneously.
Correct answer is: To execute multiple instructions simultaneously
Q.2 Which of the following is NOT a stage typically found in a 5-stage instruction pipeline?
Instruction Fetch (IF)
Instruction Decode (ID)
Execute (EX)
Memory Allocation (MA)
Explanation - The standard 5-stage pipeline consists of IF, ID, EX, Memory Access (MEM), and Write Back (WB). Memory Allocation is not a typical stage.
Correct answer is: Memory Allocation (MA)
Q.3 What is a data hazard in pipelining?
When instructions compete for CPU power
When an instruction depends on the result of a previous instruction
When instructions are executed out of order
When the CPU clock is too slow
Explanation - Data hazards occur when an instruction requires data that has not yet been computed by previous instructions in the pipeline.
Correct answer is: When an instruction depends on the result of a previous instruction
Q.4 Which technique can be used to reduce control hazards caused by branch instructions?
Operand forwarding
Branch prediction
Cache optimization
Instruction reordering
Explanation - Branch prediction tries to guess the outcome of a branch to reduce pipeline stalls caused by control hazards.
Correct answer is: Branch prediction
Q.5 What is instruction-level parallelism (ILP)?
Executing instructions sequentially without stalls
Performing multiple operations on a single instruction
Executing multiple instructions in parallel
Optimizing the memory hierarchy
Explanation - ILP refers to the ability of a CPU to execute multiple instructions simultaneously, exploiting opportunities for parallel execution within a single thread.
Correct answer is: Executing multiple instructions in parallel
Q.6 What is a structural hazard in pipelining?
When an instruction depends on a previous instruction
When two instructions require the same hardware resource
When the CPU clock slows down unexpectedly
When instructions are incorrectly predicted
Explanation - Structural hazards occur when hardware resources are insufficient to handle all instructions simultaneously, leading to pipeline stalls.
Correct answer is: When two instructions require the same hardware resource
Q.7 Which technique allows resolving data hazards without stalling the pipeline?
Operand forwarding
Loop unrolling
Branch prediction
Cache prefetching
Explanation - Operand forwarding (also called data forwarding) forwards results directly from one pipeline stage to a previous stage to avoid stalls due to data hazards.
Correct answer is: Operand forwarding
Q.8 Superscalar processors achieve ILP by:
Increasing the clock frequency
Executing more than one instruction per clock cycle
Reducing instruction memory size
Using a smaller pipeline depth
Explanation - Superscalar architectures issue multiple instructions per cycle using multiple execution units to exploit instruction-level parallelism.
Correct answer is: Executing more than one instruction per clock cycle
Q.9 Which of the following is a common method to increase instruction throughput in pipelines?
Loop unrolling
Increasing instruction set size
Using smaller registers
Reducing cache size
Explanation - Loop unrolling reduces the number of branch instructions and increases instruction-level parallelism, improving pipeline throughput.
Correct answer is: Loop unrolling
Q.10 What is a pipeline stall?
A temporary halt in instruction fetch due to resource conflicts or hazards
Execution of multiple instructions simultaneously
A permanent failure of the CPU
An increase in clock frequency
Explanation - Pipeline stalls occur when an instruction cannot proceed to the next stage due to data, control, or structural hazards.
Correct answer is: A temporary halt in instruction fetch due to resource conflicts or hazards
Q.11 Out-of-order execution helps to:
Simplify the instruction set
Increase instruction-level parallelism
Reduce memory size
Increase pipeline stalls
Explanation - Out-of-order execution allows instructions that are not dependent on others to execute ahead of stalled instructions, improving ILP.
Correct answer is: Increase instruction-level parallelism
Q.12 Which type of dependency exists when an instruction needs a value from a previous instruction?
Control dependency
Data dependency
Structural dependency
Resource dependency
Explanation - Data dependency arises when one instruction requires data generated by a prior instruction, which can cause pipeline hazards.
Correct answer is: Data dependency
Q.13 A hazard that occurs due to a branch instruction is called:
Data hazard
Control hazard
Structural hazard
Resource hazard
Explanation - Control hazards occur when the pipeline must decide the next instruction to fetch, which depends on the outcome of a branch.
Correct answer is: Control hazard
Q.14 Which of the following improves ILP without modifying hardware?
Compiler optimizations
Increasing pipeline stages
Adding more execution units
Using branch prediction hardware
Explanation - Compilers can reorder instructions, unroll loops, and schedule instructions to maximize parallelism, improving ILP at the software level.
Correct answer is: Compiler optimizations
Q.15 What does 'fetch-decode-execute' represent in pipelining?
The stages of a pipeline
A method for memory access
A type of ILP
A cache optimization technique
Explanation - Fetch-decode-execute describes the sequential stages in which instructions are processed, forming the basis of pipeline design.
Correct answer is: The stages of a pipeline
Q.16 Which of the following is a limitation of deep pipelines?
Reduced clock speed
Increased branch penalty
Lower instruction-level parallelism
Fewer pipeline stages
Explanation - Deep pipelines have more stages, so mispredicted branches cause larger penalties due to more instructions being flushed.
Correct answer is: Increased branch penalty
Q.17 Which pipeline technique allows overlapping the execution of multiple instructions?
Superscalar execution
Instruction pipelining
Vector processing
Cache memory
Explanation - Instruction pipelining divides instruction execution into stages, allowing multiple instructions to be processed simultaneously at different stages.
Correct answer is: Instruction pipelining
Q.18 A RAW hazard stands for:
Read After Write
Write After Read
Read After Read
Write After Write
Explanation - RAW (Read After Write) hazard occurs when an instruction tries to read a value before a previous instruction writes it, causing a data hazard.
Correct answer is: Read After Write
Q.19 Which mechanism is used to continue execution despite branch hazards?
Instruction prefetching
Branch prediction
Cache memory
Pipeline interleaving
Explanation - Branch prediction guesses the outcome of a branch to keep the pipeline full and minimize stalls caused by control hazards.
Correct answer is: Branch prediction
Q.20 Loop unrolling is mainly used to:
Reduce the number of instructions
Increase instruction-level parallelism
Decrease register usage
Simplify the compiler design
Explanation - Loop unrolling replicates loop bodies multiple times, reducing branch instructions and increasing opportunities for parallel execution.
Correct answer is: Increase instruction-level parallelism
Q.21 Which of these is a structural hazard example?
Two instructions need the ALU at the same time
An instruction depends on previous data
A branch misprediction occurs
An instruction fails to fetch
Explanation - Structural hazards happen when multiple instructions compete for the same hardware resource simultaneously.
Correct answer is: Two instructions need the ALU at the same time
Q.22 What is a WAW hazard?
Write After Write
Read After Write
Write After Read
Read After Read
Explanation - WAW hazard occurs when two instructions attempt to write to the same register in the wrong order, causing incorrect data.
Correct answer is: Write After Write
Q.23 How can software techniques help in reducing pipeline hazards?
By modifying the CPU hardware
By reordering instructions and scheduling
By increasing clock frequency
By decreasing memory size
Explanation - Software techniques like instruction scheduling and loop unrolling help reduce hazards by optimizing instruction sequence.
Correct answer is: By reordering instructions and scheduling
Q.24 What is the impact of increasing pipeline stages?
Higher instruction throughput but higher branch penalties
Lower instruction throughput and lower branch penalties
No change in performance
Always increases clock speed without drawbacks
Explanation - Deeper pipelines can process more instructions simultaneously but increase penalties for mispredicted branches due to more stages needing flush.
Correct answer is: Higher instruction throughput but higher branch penalties
Q.25 Which technique is most suitable for exploiting ILP in a single thread?
Superscalar execution
Multithreading
Multiprocessing
Cache optimization
Explanation - Superscalar processors execute multiple instructions per cycle from a single thread, effectively exploiting instruction-level parallelism.
Correct answer is: Superscalar execution