Q.1 What does ISA stand for in computer architecture?
Instruction Set Architecture
Internal System Access
Integrated Software Algorithm
Intelligent System Array
Explanation - ISA refers to the set of instructions that a processor can execute, defining the interface between hardware and software.
Correct answer is: Instruction Set Architecture
Q.2 Which of the following is NOT a type of ISA?
CISC
RISC
VLIW
FIFO
Explanation - CISC (Complex Instruction Set Computing), RISC (Reduced Instruction Set Computing), and VLIW (Very Long Instruction Word) are types of ISAs. FIFO is a queue management technique, not an ISA.
Correct answer is: FIFO
Q.3 RISC architecture is characterized by:
Many complex instructions
Few simple instructions
No registers
Stack-based computation only
Explanation - RISC focuses on a small number of simple instructions to achieve higher performance and efficiency.
Correct answer is: Few simple instructions
Q.4 CISC architectures are known for:
Complex instructions with variable execution time
Simple instructions with fixed execution time
No memory access
Single-cycle execution for all instructions
Explanation - CISC provides rich instructions that can execute complex tasks but may take multiple cycles, unlike RISC.
Correct answer is: Complex instructions with variable execution time
Q.5 In ISA, an instruction that moves data from memory to a register is called:
STORE
LOAD
JUMP
ADD
Explanation - LOAD instructions transfer data from memory to a register, while STORE transfers from a register to memory.
Correct answer is: LOAD
Q.6 Which ISA type generally uses more registers?
RISC
CISC
Stack-based ISA
None of the above
Explanation - RISC architectures rely heavily on registers for operations to maintain simple instructions and fast execution.
Correct answer is: RISC
Q.7 VLIW in ISA stands for:
Very Long Instruction Word
Variable Length Instruction Word
Virtual Logical Instruction Width
Verified Linear Instruction Workflow
Explanation - VLIW uses long instruction words that contain multiple operations to be executed in parallel.
Correct answer is: Very Long Instruction Word
Q.8 Which of the following determines how an instruction is executed by the CPU?
ISA
Compiler
Operating System
Linker
Explanation - The ISA defines the set of instructions and their execution model, which guides the CPU on how to perform operations.
Correct answer is: ISA
Q.9 In a load/store architecture, arithmetic operations are performed only on:
Memory locations
Registers
Cache only
Stack only
Explanation - Load/store architectures (typical in RISC) require data to be loaded into registers before performing arithmetic operations.
Correct answer is: Registers
Q.10 Which ISA characteristic affects the speed of execution the most?
Number of instructions
Instruction format complexity
Clock speed of CPU
Compiler efficiency
Explanation - Simpler instruction formats generally allow faster decoding and execution, as seen in RISC architectures.
Correct answer is: Instruction format complexity
Q.11 Immediate addressing in ISA means:
Data is in memory
Data is in register
Data is part of the instruction itself
Data is on stack
Explanation - Immediate addressing embeds the operand directly in the instruction, allowing faster access without memory or register lookup.
Correct answer is: Data is part of the instruction itself
Q.12 Which of the following is a stack-based ISA example?
Intel x86
Java Virtual Machine
ARM
MIPS
Explanation - JVM uses a stack-based instruction set, where operations are performed on the top elements of the operand stack.
Correct answer is: Java Virtual Machine
Q.13 How many operands do typical RISC instructions have?
One
Two
Three
Four
Explanation - Most RISC instructions are of the form: OP destination, source1, source2.
Correct answer is: Three
Q.14 Which is generally more memory efficient?
CISC
RISC
VLIW
Stack ISA
Explanation - CISC instructions can perform complex operations in a single instruction, often reducing code size.
Correct answer is: CISC
Q.15 In ISA, a branch instruction is used for:
Data transfer
Conditional or unconditional jump
Arithmetic operation
Logical operation
Explanation - Branch instructions change the sequence of execution based on conditions or unconditionally.
Correct answer is: Conditional or unconditional jump
Q.16 Which of the following is true about fixed-length instructions?
Easier to decode
More flexible than variable length
Only used in CISC
Never used in RISC
Explanation - Fixed-length instructions simplify decoding because the CPU knows the instruction size in advance.
Correct answer is: Easier to decode
Q.17 Which ISA is commonly used in modern smartphones?
x86
ARM
MIPS
SPARC
Explanation - ARM is a RISC-based ISA optimized for low power consumption, widely used in mobile devices.
Correct answer is: ARM
Q.18 Micro-operations in a CPU are closely related to:
ISA instructions
Clock cycles
Memory hierarchy
Compiler optimization
Explanation - ISA instructions are broken into micro-operations that control the actual hardware steps to execute the instruction.
Correct answer is: ISA instructions
Q.19 In a CISC processor, instruction decoding is usually:
Simple and fast
Complex and slow
Done by compiler
Not required
Explanation - CISC instructions vary in length and complexity, making the decoding stage more complicated compared to RISC.
Correct answer is: Complex and slow
Q.20 Which type of ISA typically requires more RAM for instruction storage?
RISC
CISC
Stack-based
VLIW
Explanation - RISC uses simpler instructions but often requires more instructions for the same operation, increasing memory usage.
Correct answer is: RISC
Q.21 What is the purpose of the opcode in an instruction?
Specifies the operation to be performed
Specifies the memory address
Specifies register contents
Specifies the program counter value
Explanation - The opcode part of an instruction tells the CPU which operation (ADD, SUB, LOAD, etc.) to execute.
Correct answer is: Specifies the operation to be performed
Q.22 Which ISA type often requires pipelining for high performance?
RISC
CISC
Stack-based
None of the above
Explanation - RISC architectures benefit from pipelining because their instructions are simple and uniform, enabling faster instruction throughput.
Correct answer is: RISC
Q.23 Register-to-register operations are a characteristic of which architecture?
Load/store (RISC)
Memory-to-memory (CISC)
Stack-based
VLIW
Explanation - In RISC, arithmetic and logical operations are performed only between registers; memory access is done through explicit LOAD and STORE instructions.
Correct answer is: Load/store (RISC)
Q.24 Which ISA design emphasizes minimizing the number of cycles per instruction?
RISC
CISC
Stack-based
VLIW
Explanation - RISC focuses on executing each instruction in fewer cycles using simple and uniform instruction formats.
Correct answer is: RISC
Q.25 In ISA, addressing modes define:
How to access operands
Instruction length
Register type
Clock frequency
Explanation - Addressing modes specify how the instruction identifies the operands, whether in memory, register, or immediate value.
Correct answer is: How to access operands